Massachusetts
Institute
of
Technology
Department
of
Electrical
Engineering
and
Computer
Science
6.976
High
Speed
Communication
Circuits
and
Systems
Spring
2003
Homework
#5:
Voltage
Controlled
Oscillators
c
Copyright
�
2003
by
Michael
H.
Perrott
Reading:
Chapters
16
and
17
of
Thomas
H.
Lee’s
book.
Chapter
7
of
Behzad
Razavi’s
book.
1. The
following
is
based
on
Problem
4
in
Chapter
16
of
Thomas
Lee’s
book,
and
considers
the
differential
CMOS
VCO
shown
in
Figure
1.
Assume
the
bulk
nodes
of
the
PMOS
and
NMOS
are
tied
to
their
respective
source
nodes.
A
M
1
M
2
M
3
V
out
C
tune
3 nH
100/0.18
50/0.18
M
4
100/0.18
50/0.18
V
out
V
in
I
bias
V
dd
=1.8 V
0 V
Figure
1:
Differential
CMOS
LC
Oscillator.
(a) Neglecting
transistor
capacitances,
calculate
the
oscillation
frequency
assuming
C
tune
has
been
adjusted
to
a
value
of
2
pF.
(b) Using
Hspice
and
the
mos018.mod
MOS
models,
determine
the
minimum
value
of
bias
current,
I
bias
,
such
that
sustained
oscillation
can
be
achieved
in
the
tank.
Assume
an
inductor
with
Q
=10
at
the
oscillation
frequency
is
the
only
source
of
loss
in
the
tank.
1
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(c) Using
minimum
I
bias
,
extract
the
transistor
capacitances
and
determine
the
new
oscillation
frequency.
By
how
much
did
the
frequency
shift
from
that
found
in
part
(a)?
(d) Calculate
the
oscillation
amplitude,
A
,
as
a
function
of
I
bias
under
the
assumption
that
the
current
waveforms
through
the
transistors
are
square
waves,
and
that
the
oscillator
is
in
the
currentlimited
regime.
(e) Assuming
that
the
tank
abruptly
shifts
to
the
voltagelimited
regime
when
the
oscillator
amplitude
equals
half
the
supply
voltage
(
V
dd
),
determine
the
value
of
I
bias
for
which
the
phase
noise
of
the
oscillator
will
be
minimized.
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 Spring '03
 MICHAELPERROTT
 Hertz, Volt, Electronic oscillator, phase noise, Ibias, Thomas H. Lee

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