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# proj1 - Massachusetts Institute of Technology Department of...

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Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.976 High Speed Communication Circuits and Systems Spring 2003 Project #1: Design of a High Speed Divide-by-32/33 Prescaler Passed Out: March 21, 2003 Due: April 11, 2003 Copyright c 2003 by Michael H. Perrott 1 Objective This project will introduce you to the art of designing high speed frequency dividers. Your goal will be to design a divide-by-32/33 prescaler, as shown in Figure 1, that supports a minimum input frequency of 5 GHz with maximum power dissipation of 10 mW. Calculation of power dissipation must include all blocks in Figure 1 (including bias sources) except for input voltage sources V in and V in . You should strive to exceed one of these specifications such that You achieve an input frequency higher than 5 GHz with power dissipation not exceeding 10 mW, OR You achieve power dissipation less than 10 mW with an input frequency equal to or above 5 GHz. In other words, you should explore either a high speed or low power approach under the given constraints. C load =100 fF V in 32/33 V in 50 50 1.8 V 0.9 V 5 GHz 1 T < IN IN 32/33 OUT 1.8 V 0.9 V rise/fall time = 40 ps D Q Reg CON OUT Figure 1: High Speed Divide-by-32/33 Circuit. 1

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2 Report Your report should consist of the sections described below. Note that one report is turned in for each project team (consisting of exactly 2 people), and must be no longer than 15 pages including all plots and figures. A brief introduction of the project and a statement of your overall goal (i.e., a high speed or low power divider design) A brief summary of the performance you achieved, which includes a table of the val- ues you obtained for the following specifications (assume a temperature of 25 degrees Celsius except where otherwise stated): 1. Maximum input frequency of overall divider At 25 degrees Celsius At 0 degrees Celsius At 80 degrees Celsisus 2. Maximum input frequency achieved by each major section of the divider (i.e., the front end divider circuit, the differential-to-full swing circuit (if used), and the back end divider circuits) 3. Total power dissipation (including bias sources) 4. A breakdown of power dissipation in the divider (i.e., list the power consumed for each major block in the divider) 5. Overall speed/power metric for the entire divider (i.e., Maximum speed (GHz)/Power
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proj1 - Massachusetts Institute of Technology Department of...

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