Verilog-Background.pptx

# Verilog-Background.pptx - EE 2730 Fall 2009 Verilog Review...

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EE 2730 Fall 2009 Verilog Review for Combinational Circuits Chapter 2.9, 2.10, 4.12, 5.5, 6.6, Appendix A Adapted from a presentation by Dr. Jerry L. Trahan EE 2730 - Fall 2009

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source: Brown and 2 Structural specification f x 3 x 1 x 2 Figure 2.30. A simple logic function. module example1 (x1, x2, x3, f); input x1, x2, x3; output f; and (g, x1, x2); not (k, x2); and (h, k, x3); or (f, g, h); endmodule Figure 2.31. Verilog code for the circuit in Figure 2.30.
source: Brown and 3 Behavioral specification f x 3 x 1 x 2 Figure 2.30. A simple logic function. module example3 (x1, x2, x3, f); input x1, x2, x3; output f ; assign f = (x1 & x2) | (~x2 & x3); endmodule Figure 2.34. Using the continuous assignment to specify the circuit in Figure 2.30.

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Brown and 4 Behavioral specification 2 module example3 (x1, x2, x3, f); input x1, x2, x3; output f ; assign f = (x1 & x2) | (~x2 & x3); endmodule Figure 2.34. Using the continuous assignment to specify the circuit in Figure 2.30. // Behavioral specification module example5 (x1, x2, x3, f); input x1, x2, x3; output f ; reg f ; always @(x1 or x2 or x3) if (x2 == 1) f = x1; else f = x3; endmodule Figure 2.36. Behavioral specification of the circuit in Figure 2.30 using a procedural statement. sensitivity list
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## This document was uploaded on 11/01/2011 for the course EE 2730 at LSU.

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Verilog-Background.pptx - EE 2730 Fall 2009 Verilog Review...

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