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Design - EE 2730 Spring 2010 Design of Sequential Circuits...

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EE 2730 Spring 2010 Design of Sequential Circuits Chapter 8.1-8.3, 8.6-8.8 EE 2730 - Spring 2010

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Synchronous Sequential Circuit Structure EE 2730 - Spring 2010 Combinational circuit Flip-flops Clock Q W Z Combinational circuit state excitation excitation logic o Next state and present output depend on n Present state n Present input Mealy Machine o Sequential circuit o Finite State Machine (FSM) o (simply) Machine output logic external input output
Synchronous Sequential Circuit Structure EE 2730 - Spring 2010 Combinational circuit Flip-flops Clock Q W Z Combinational circuit state excitation excitation logic o Next state depends on n Present state n Present input o Present output depends only on n Present state Moore Machine output logic external input output

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Analysis Steps o Start with a Circuit o Derive Excitation Equations o Derive Next state Equations o Derive Output Equations o Construct state table o Draw state diagram o Assign symbolic names to states o Interpret state table EE 2730 - Spring 2010
o Start with a circuit o Derive Excitation Equations o Derive Next state Equations o Derive Output Equations o Construct state table o Draw state diagram o Assign symbolic names to states o Interpret state table Analysis and Design o Start with a circuit o Derive Excitation Equations o Derive Next state Equations o Derive Output Equations o Construct state table o Draw state diagram o Assign symbolic names to states o Interpret state table EE 2730 - Spring 2010 o Obtain specs o Construct a state diagram o Construct a state table o State minimization o State Assignment o Select flip-flop type(s) o Derive next state logic equations o Derive output logic equations o Implement circuit

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A Sequence Detector Example Specifications o Design a circuit with one input w and one output z. o All changes occur at the positive edge of a clock. o Output z = 1 if and only if the at the two preceding clocks, input w = 1 . o Circuit detects 11 EE 2730 - Spring 2010 Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 0 1 0 0 1 1 0
State Diagram o Circuit needs to remember if it has received two successive ones in the last two cycles n 3 states o “Got 11” o “Got 1” o “Got zip” n Present input is used the next time around n Moore machine with z = 1 associated with “Got 11.” o Circuit detects 11 EE 2730 - Spring 2010 Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 0 1 0 0 1 1 0

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State Diagram Circuit detects 11 EE 2730 - Spring 2010 Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 0 1 0 0 1 1 0 C z 1 = Reset B z 0 = A z 0 = w 0 = w 1 = w 1 = w 0 = w 0 = w 1 =
State Table Circuit detects 11 EE 2730 - Spring 2010 Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 0 1 0 0 1 1 0 Present Next state Output state w = 0 w = 1 z A A B 0 B A C 0 C A C 1 C z 1 = Reset B z 0 = A z 0 = w 0 = w 1 = w 1 = w 0 = w 0 = w 1 =

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Design - EE 2730 Spring 2010 Design of Sequential Circuits...

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