Proj1 - The fault should be s-a-0 for the internal line c 4...

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ECE 631: Digital System Testing and Testable Design Project #1 Assignment Generate a VHDL or Verilog model for the logic in the diagram in Figure 4.43 of Jha and Gupta’s book. Call the model dut.vhd (VHDL) or dut.v (verilog), where “dut” stands for “device under test”. The inputs to the model should be the primary inputs (prim_in(n), n = 0 to 4), where x 1 is prim_in(0), x 2 is prim_in(1), etc. The outputs of the model should be: 1) The primary output (prim_out) 2) The internal circuit lines (inter_node(n), n = 0 to 9), where c 1 is inter_node(0), etc. Use a “generic” to switch the DUT model between good and faulty.
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Unformatted text preview: The fault should be s-a-0 for the internal line c 4 (note that this is different that the book example). Use the D-algorithm to determine a test for the s-a-0 fault (hand calculation). Write a test bench (called t_dut.vhd or t_dut.v) for the DUT model. The test bench should apply the test found using the D-algorithm. Run the test bench for the DUT model for the following two cases: 1) The good/faulty generic switch is set to good. 2) The good/faulty generic switch is set to faulty. Plot all input and output signals of the DUT model (including internal nodes)....
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This document was uploaded on 11/01/2011 for the course ECE 631 at Boise State.

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