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# Proj2 - carry and then 8 times to do the add Be sure that...

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1 ECE 631: Digital Systems Test and Testable Design Project #2 Use time-frame expansion and the extended D-algorithm to find a test for the s-a-0 fault in the sequential circuit shown below. A(n) and B(n) are the two primary inputs (x 1 and x 2 in the notation of the book). S(n) and C(n+1) are the two primary outputs (z 1 and z 2 in the notation of the book). Remember that the faulty circuit has the same fault in every copy of the combinational logic. It is necessary to stimulate at least one of these faults to have a test - it is not necessary to stimulate the fault in every copy of the expanded faulty circuit (although every copy of the faulty gate should give faulty output). There are no faults in any copy of the fault-free circuit. The circuit is a full adder configured to be used as a ripple-carry adder. Suppose that this circuit is part of an 8-bit microcontroller. Under normal operation, this circuit would be cycled 9 times to do an add (once with input 00 to clear the

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Unformatted text preview: carry and then 8 times to do the add). Be sure that the test you find works the same whether the initial carry value C(0) is 0 or 1. This can be accomplished by being sure that C(n) is set to X at the start of the test generation. Alternatively, one could set C(n) to 0 initially and use the extended D-algorithm to find a test. Then C(n) would be initialized to 1 and the output from the test pattern would be examined to see if the error on at least one primary output was the same for C(0) = 0 and C(0) = 1. In order for the error to be the same it should be D in both cases or D-bar in both cases (on the same primary output). Show simulation output proving that your test works for both initial values of the carry bit. 2 s-a-0 A ( n ) S ( n ) B ( n ) C ( n + 1 ) C ( n ) F F...
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