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Unformatted text preview: YNW%jE;awﬂ” Boise State University
Department of Electrical and Computer Engineering
ECE 230 Digital Systems
Test 2, Date: April 6, 2009, Location: ET 110, Time: 1:40pm to 2: 0pm / Name: Instructions: Show all steps and logic circuits for full or partial credits. It is very important that you write clearly,
so that your test can be graded appropriately and fairly. This is a closed book and closed notes test. ABSOL U T EL Y N 0 calculator. ,. Maw Ma 2% it WC)” 1. (15 points) Complete the following using 8bit signed number (usin 2’s complement) representation. You need to indicate whether arithmetic overﬂow occurs. What is the range of 8—bit signed number using 2’scgjiplement
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rugs km???” ,\1% i K\\b\0\ / 2. (10 points) Short answers and ﬁll in the blanks. V 3m
a. What is the key di f rence between a halfadder and fulladder? my v6
b. Latch is \W sensitive.
c. Flip~ﬂop is ‘ se sitive.
d. A multiplexer circuit h s a number of 420315 inputs, one or more select inputs, and output.
e. Why is 2’3 complement better for im le enting arithmetic logics than 1’5 comp ment?‘ ‘ w; l
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WA 3. (10 points) Show how the functionf= W2 +W‘W3 +w,w2 can be realized using Act 1 logic blocks (Act l logic
block is shown). Note that there are no NOT gates in the chip; hence complements of signals have to be generated using the multiplexers in the logic block. .. m a. ( M k M N 1
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"X “a so Ob 5. (15 points) Design a comparator logic circuit that compares two 4—bit binary numbers (A and B). This comparator
logic only has 1—bit output (called AltB, A less than B). When A < B, AltB = 1. Otherwise, AltB = O. 2 of2 ...
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This document was uploaded on 11/01/2011 for the course ECE 230 at Boise State.
 Spring '08
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