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Unformatted text preview: Altera Corporation 11–1 November 2006 11. PIO Core with Avalon Interface Core Overview The parallel input/output (PIO) core provides a memory-mapped interface between an Avalon ® Memory-Mapped (Avalon-MM) slave port and general-purpose I/O ports. The I/O ports connect either to on-chip user logic, or to I/O pins that connect to devices external to the FPGA. The PIO core provides easy I/O access to user logic or external devices in situations where a “bit banging” approach is sufficient. Some example uses are: ■ Controlling LEDs ■ Acquiring data from switches ■ Controlling display devices ■ Configuring and communicating with off-chip devices, such as application-specific standard products (ASSP) The PIO core interrupt request (IRQ) output can assert an interrupt based on input signals. The PIO core is SOPC Builder ready and integrates easily into any SOPC Builder-generated system. Functional Description Each PIO core can provide up to 32 I/O ports. An intelligent host such as a microprocessor controls the PIO ports by reading and writing the register-mapped Avalon-MM interface. Under control of the host, the PIO core captures data on its inputs and drives data to its outputs. When the PIO ports are connected directly to I/O pins, the host can tristate the pins by writing control registers in the PIO core. Figure 11–1 shows an example of a processor-based system that uses multiple PIO cores to blink LEDs, capture edges from on-chip reset-request control logic, and control an off-chip LCD display. NII51007-6.1.0 11–2 Altera Corporation November 2006 Quartus II Handbook, Volume 5 Figure 11–1. An Example System Using Multiple PIO Cores When integrated into an SOPC Builder-generated system, the PIO core has two user-visible features: ■ A memory-mapped register space with four registers: data , direction , interruptmask , and edgecapture . ■ 1 to 32 I/O ports. The I/O ports can be connected to logic inside the FPGA, or to device pins that connect to off-chip devices. The registers provide an interface to the I/O ports via the Avalon-MM interface. See Table 11–2 on page 11–7 for a description of the registers. Some registers are not necessary in certain hardware configurations, in which case the unnecessary registers do not exist. Reading a non-existent register returns an undefined value, and writing a non-existent register has no effect. Data Input & Output The PIO core I/O ports can connect to either on-chip or off-chip logic. The core can be configured with inputs only, outputs only, or both inputs and outputs. If the core will be used to control bidirectional I/O pins on the device, the core provides a bidirectional mode with tristate control....
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- Fall '08
- Interrupt, Input/output, Altera Corporation, Nios II