n2cpu_nii51008

n2cpu_nii51008 - 12. Timer Core with Avalon Interface...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
Altera Corporation 12–1 November 2006 12. Timer Core with Avalon Interface Core Overview The timer core with Avalon ® interface core is a 32-bit interval timer for Avalon-based processor systems, such as a Nios ® II processor system. The timer provides the following features: Controls to start, stop, and reset the timer Two count modes: count down once and continuous count-down Count-down period register Maskable interrupt request (IRQ) upon reaching zero Optional watchdog timer feature that resets the system if timer ever reaches zero Optional periodic pulse generator feature that outputs a pulse when timer reaches zero Compatible with 32-bit and 16-bit processors Device drivers are provided in the HAL system library for the Nios II processor. The timer core is SOPC Builder-ready and integrates easily into any SOPC Builder-generated system. Functional Description Figure 12–1 shows a block diagram of the timer core. Figure 12–1. Timer Core Block Diagram Register File status control periodl snapl periodh snaph IRQ Address, data, etc. Avalon-MM slave interface to on-chip logic Control Logic resetrequest (watchdog) timeout_pulse Counter NII51008-6.1.0
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
12–2 Altera Corporation November 2006 Quartus II Handbook, Volume 5 The timer core has two user-visible features: The Avalon Memory-Mapped (Avalon-MM) interface that provides access to six 16-bit registers An optional pulse output that can be used as a periodic pulse generator All registers are 16-bits wide, making the timer compatible with both 16- bit and 32-bit processors. Certain registers only exist in hardware for a given configuration. For example, if the timer is configured with a fixed period, the period registers do not exist in hardware. The basic behavior of the timer is described below: An Avalon-MM master peripheral, such as a Nios II processor, writes the timer core’s control register to: Start and stop the timer Enable/disable the IRQ Specify count-down once or continuous count-down mode A processor reads the status register for information about current timer activity. A processor can specify the timer period by writing a value to the period registers, periodl and periodh . An internal counter counts down to zero, and whenever it reaches zero, it is immediately reloaded from the period registers. A processor can read the current counter value by first writing to either snapl or snaph to request a coherent snapshot of the counter, and then reading snapl and snaph for the full 32-bit value. When the count reaches zero: If IRQs are enabled, an IRQ is generated The (optional) pulse-generator output is asserted for one clock period The (optional) watchdog output resets the system Avalon-MM Slave Interface The timer core implements a simple Avalon-MM slave interface to provide access to the register file. The Avalon-MM slave port uses the resetrequest signal to implement watchdog timer behavior. This
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This document was uploaded on 11/01/2011 for the course EE 492 at Boise State.

Page1 / 10

n2cpu_nii51008 - 12. Timer Core with Avalon Interface...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online