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Unformatted text preview: Altera Corporation 51 November 2006 5. JTAG UART Core with Avalon Interface Core Overview The JTAG universal asynchronous receiver/transmitter (UART) core with Avalon interface implements a method to communicate serial character streams between a host PC and an SOPC Builder system on an Altera FPGA. In many designs, the JTAG UART core eliminates the need for a separate RS-232 serial connection to a host PC for character I/O. The core provides a simple register-mapped Avalon interface that hides the complexities of the JTAG interface from embedded software programmers. Master peripherals (such as a Nios II processor) communicate with the core by reading and writing control and data registers. The JTAG UART core uses the JTAG circuitry built in to Altera FPGAs, and provides host access via the JTAG pins on the FPGA. The host PC can connect to the FPGA via any Altera JTAG download cable, such as the USB-Blaster cable. Software support for the JTAG UART core is provided by Altera. For the Nios II processor, device drivers are provided in the HAL system library, allowing software to access the core using the ANSI C Standard Library stdio.h routines. For the host PC, Altera provides JTAG terminal software that manages the connection to the target, decodes the JTAG data stream, and displays characters on screen. The JTAG UART core is SOPC Builder-ready and integrates easily into any SOPC Builder-generated system. Functional Description Figure 51 shows a block diagram of the JTAG UART core and its connection to the JTAG circuitry inside an Altera FPGA. The following sections describe the components of the core. NII51009-6.1.0 52 Altera Corporation November 2006 Quartus II Handbook, Volume 5 Figure 51. JTAG UART Core Block Diagram Avalon Slave Interface & Registers The JTAG UART core provides an Avalon slave interface to the JTAG circuitry on an Altera FPGA. The user-visible interface to the JTAG UART core consists of two 32-bit registers, data and control , that are accessed through an Avalon slave port. An Avalon master, such as a Nios II processor, accesses the registers to control the core and transfer data over the JTAG connection. The core operates on 8-bit units of data at a time; eight bits of the data register serve as a one-character payload. The JTAG UART core provides an active-high interrupt output that can request an interrupt when read data is available, or when the write FIFO is ready for data. For further details see Interrupt Behavior on page 513 . Read & Write FIFOs The JTAG UART core provides bidirectional FIFOs to improve bandwidth over the JTAG connection. The FIFO depth is parameterizable to accommodate the available on-chip memory. The FIFOs can be constructed out of memory blocks or registers, allowing designers to trade off logic resources for memory resources, if necessary....
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- Fall '08