n2cpu_nii51010

n2cpu_nii51010 - Altera Corporation 61 November 2006 6....

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Unformatted text preview: Altera Corporation 61 November 2006 6. UART Core with Avalon Interface Core Overview The universal asynchronous receiver/transmitter core with Avalon interface (the UART core) implements a method to communicate serial character streams between an embedded system on an Altera FPGA and an external device. The core implements the RS-232 protocol timing, and provides adjustable baud rate, parity, stop and data bits, and optional RTS / CTS flow control signals. The feature set is configurable, allowing designers to implement just the necessary functionality for a given system. The core provides a simple register-mapped Avalon Memory-Mapped (Avalon-MM) slave interface that allows Avalon-MM master peripherals (such as a Nios II processor) to communicate with the core simply by reading and writing control and data registers. The UART core is SOPC Builder-ready and integrates easily into any SOPC Builder-generated system. NII51010-6.1.0 62 Altera Corporation November 2006 Quartus II Handbook, Volume 5 Functional Description Figure 61 shows a block diagram of the UART core. Figure 61. Block Diagram of the UART Core in a Typical System The core has two user-visible parts: The register file, which is accessed via the Avalon-MM slave port The RS-232 signals, RXD , TXD , CTS , and RTS Avalon-MM Slave Interface & Registers The UART core provides an Avalon-MM slave interface to the internal register file. The user interface to the UART core consists of six 16-bit registers: control , status , rxdata , txdata , divisor , and endofpacket . A master peripheral, such as a Nios II processor, accesses the registers to control the core and transfer data over the serial connection. The UART core provides an active-high interrupt request (IRQ) output that can request an interrupt when new data has been received, or when the core is ready to transmit another character. For further details see Interrupt Behavior on page 620 . Altera FPGA UART Core baud rate divisor shift register RXD RTS CTS TXD L e v e l S h i f t e r R S- 2 3 2 C o n n e c t o r Avalon-MM signals connected to on-chip logic data IRQ dataavailable readyfordata endofpacket address clock rxdata status control txdata endofpacket shift register divisor Altera Corporation 63 November 2006 UART Core with Avalon Interface The Avalon-MM slave port is capable of transfers with flow control. The UART core can be used in conjunction with a direct memory access (DMA) peripheral with Avalon-MM flow control to automate continuous data transfers between, for example, the UART core and memory. f See the Timer Core with Avalon Interface chapter for details. See the Avalon Memory-Mapped Interface Specification for details of the Avalon-MM interface....
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n2cpu_nii51010 - Altera Corporation 61 November 2006 6....

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