ECE230_S11_Lab9_Readme

ECE230_S11_Lab9_Readme - Digital Systems Laboratory ECE230L...

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Digital Systems Laboratory Draft Lab 9 ECE230L – Spring 2011 Boise State University Electrical and Computer Engineering Department Page 1 of 5 Lab 9: Introduction to Sequential Design Objective: Transition from combinational to sequential circuit design. Lab Details : A. Below is an implementation of a gated D latch, found in figure 7.8 from your reference text (pg. 391). Using Xilinx schematic capture, duplicate this circuit and use traditional combinational test bench methods to test the circuit. Build a table of test cases that will completely exercise the circuit. For every case, determine what the expected value should be. (If you consider the fact that a signal could change its value at any point in time, you should have a total of 16 cases - but when applied to the fact that Q can have two possible states, the total cases are then 32.) If you don’t test for all 32 cases, write a justification as to why a smaller number of test cases is adequate to completely exercise the circuit. Your test bench should show all internal signals (give them a good name and show on wave form). Implement the design on the Basys2 board by assigning the two inputs C and D to switches, and the
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This document was uploaded on 11/02/2011 for the course ECE 230 at Boise State.

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ECE230_S11_Lab9_Readme - Digital Systems Laboratory ECE230L...

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