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Unformatted text preview: Digital Systems Laboratory Lab 11 ECE230L Spring 2011 Boise State University Electrical and Computer Engineering Department Page 1 of 2 Lab 11: Sequence Detector Objective: At the completion of this laboratory, you will know how to design a state-machine sequence detector. Lab Details : 1. Each team will be given a different problem to solve. You will be assigned your sequence during lecture period. 2. Design a sequence detector (has to be a state machine, shifting version is not allowed!) to detect occurrence of your assigned sequence. The inputs to the sequence detector are w, rst, and clk. The only output is z, to indicate the occurrence of your sequence. The inputs and output are 1-bit wide. Configure your design to be active on a positive clock edge. When your sequence is detected in the incoming string of bits, the output z goes to 1. Otherwise it will stay at 0. For example: If you are looking for the sequence 1010 and you have the input sequence 00010100010001011, the right bit is the first bit sent to the detector. In this string of bits, there are 00010100010001011, the right bit is the first bit sent to the detector....
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This document was uploaded on 11/02/2011 for the course ECE 230 at Boise State.
- Spring '08