05_Lecutre

05_Lecutre - Lecture 5 EE114 Lecture 5 Gain and Biasing...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
Lecture 5 EE114 R. Dutton, B. Murmann 1 EE114 Lecture 5 Gain and Biasing Considerations Finite Output Resistance R. Dutton, B. Murmann Stanford University R. Dutton, B. Murmann 2 Common Source Amplifier Revisited Interesting question – How much voltage gain can we get from this circuit? EE114 I D +i d V O +v o V DD v i V I R R g A m v ! =
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Lecture 5 EE114 R. Dutton, B. Murmann 3 Upper Bound on Gain (1) Plug in expression for g m EE 214 Lecture 3 L OV D L m v R V I R g A 2 ! = ! = For operation in the saturation region, we definitely require DD D V R I < Therefore, we have OV DD v V V A 2 < This is an upper bound only, useful for back of the envelope calculations (and job interviews) – Important to note that this expression does not hold with equality R. Dutton, B. Murmann 4 Upper Bound on Gain (2) The above derived upper bound comes for the fact that both gain and bias point depend on R – Want large R for large gain – Want small R to prevent device from entering triode region The upper bound may not be a serious issue in some circuits – Nonetheless it is interesting and insightful to think about ways around the issue We’ll do this graphically using “load line” plots EE 214 Lecture 3
Background image of page 2
Lecture 5 EE114 R. Dutton, B. Murmann 5 Construction of Load Line Plot EE 214 Lecture 3 I d V o V DD R I r V i R V V I o DD r ! = I r V o V o I D I d i d = g m v i R. Dutton, B. Murmann 6 Putting Things Together EE114 I r , I d V o Operating point V DD V DD /R i d = g m v i v o
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Lecture 5 EE114 R. Dutton, B. Murmann 7 Larger Resistance EE114 I r , I d V o V DD V DD /R small i d = g m v i v o V DD /R large R. Dutton, B. Murmann 8 Discussion The issue with this configuration is that the load line is pinned to the point (V DD , 0) Larger V DD allows use of larger R and therefore larger gain – This is also evident from the equation on slide 3 It is possible to overcome this limitation by adding additional degrees of freedom; consider e.g. the following alternative load network EE114 V o V DD R I r V o V B R I x I B I x V o I B V B B o B x I R V V I + !
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 14

05_Lecutre - Lecture 5 EE114 Lecture 5 Gain and Biasing...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online