07_Lecutre

07_Lecutre - L e c tu r e 7 E x t r in s ic C a p a c it a...

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R. Dutton, B. Murmann 1 Lecture 7 Extrinsic Capacitance R. Dutton, B. Murmann Stanford University
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R. Dutton, B. Murmann 2 Extrinsic Capacitance Overlap capacitance – Gate to source and gate to drain Junction capacitance – Source to bulk and drain to bulk C jdb C jsb C ov C ov
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R. Dutton, B. Murmann 3 Overlap Capacitance Two components – Direct overlap ~ C ox WL overlap – Additional component due to fringing field • Non-negligible in modern technology (gate thickness is large compared to other feature sizes) Simple model equation C ov = C ov ' · W EE114 technology: – C ov '= 0.5fF/ μ m for both NMOS and PMOS – Spice model parameters: CGSO=0.5n, CGDO=0.5n
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R. Dutton, B. Murmann 4 Junction Capacitance (1) Two components: – Area (AS, AD) and Perimeter (PS, PD) capacitance L L diff L diff G S D W AS = W L diff PS = W + 2L diff AD = W L diff PD = W + 2L diff EE114 technology: L diff = 3 μ m
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R. Dutton, B. Murmann 5 Junction Capacitance (2) MJSW DB MJ DB jdb PB V CJSW PD PB V CJ AD C ! " # $ % & + + ! " # $ % & + = 1 1 EE114 Technology CJ CJSW MJ MJSW PB NMOS 0.1 fF/ μ m 2 0.5 fF/ μ m 0.5 0.33 0.95V PMOS 0.3 fF/ μ m 2 0.35 fF/ μ m 0.5 0.33 0.95V MJSW SB MJ SB jsb PB V CJSW PS PB V CJ AS C ! " # $ % & + + ! " # $ % & + = 1 1
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R. Dutton, B. Murmann 6 Junction Capacitance in Spice (1) There are two ways to handle junction capacitance in Spice The first one is to compute AS, AD, PS, PD manually for each MOSFET (tedious…) *** netlist *... *... *** model .model my_nmos nmos kp=50u vto=0.5 lambda=0.1 cox=2.3e-3 capop=1 + cgdo=0.5n cgso=0.5n cj=0.1m cjsw=0.5n pb=0.95 mj=0.5 mjsw=0.33 pbsw=0.95
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R. Dutton, B. Murmann 7 Junction Capacitance in Spice (2)
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This note was uploaded on 11/02/2011 for the course EE 114 taught by Professor Murmann during the Fall '08 term at Stanford.

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07_Lecutre - L e c tu r e 7 E x t r in s ic C a p a c it a...

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