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10_Lecutre - EE114 Lecture 10 Lecture 10 Backgate Effect...

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EE114 Lecture 10 R. Dutton, B. Murmann 1 EE114 (HO #14) Lecture 10 Backgate Effect Common Gate Stage R. Dutton, B. Murmann Stanford University R. Dutton, B. Murmann 2 EE114 (HO #14) The "Atoms" of Analog Circuit Design As we've seen from the discussion so far, a common source stage is sufficient for building a simple amplifier – How about the other two possible configurations? We'll find that common gate and drain stages can be incorporated as valuable add-ons, for building "better" amplifiers Interestingly, many analog circuits can be decomposed into a combination of the above three fundamental building blocks Common Source Common Gate Common Drain
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EE114 Lecture 10 R. Dutton, B. Murmann 3 EE114 (HO #14) Bulk Connection In the EE114 (N-well) technology, only the PMOS device has an isolated bulk connection Newer technologies * (e.g. 0.13 μ m CMOS) also tend to have NMOS devices with isolated bulk ("tripple-well" process) * Be aware : •Ask the tech. folks •Know what it means! R. Dutton, B. Murmann 4 Aside: Modern Triple-Well Process EE114 (HO #14) Courtesy Shoichi Masui n+ p+ p+ Different grounding (digital vs. analog) helps reduce noise coupling
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EE114 Lecture 10 R. Dutton, B. Murmann 5 EE114 (HO #14) Bulk Connection Scenarios Can connect bulk to source or V DD V DD NMOS PMOS R. Dutton, B. Murmann 6 PMOS Well Capacitance In the EE114 (N-well) technology, the PMOS transistor is a 5-terminal device – G, D, S, B, Substrate N-well forms a PN junction with the substrate – Often "AC shorted" when N-well=V DD , Substrate=GND – Not shorted when we connect N-well to source! • Resulting capacitance ~ 0.05 fF/ μ m 2 • Not modeled in Spice! Must add extra diode manually in this case " EE114 (HO #14)
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EE114 Lecture 10 R. Dutton, B. Murmann 7 Model for PMOS Well Capacitance Model available in ee114_hspice.sp * well-to-substrate diode * example instantiation (area = 10um*10um = 100pm^2) * (anode) (cathode) (model) (area) * d1 sub_node well_node dwell 100p .model dwell d cj0=1e-4 m=0.5 EE114 (HO #14) R. Dutton, B. Murmann 8 Well Area Estimation
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This note was uploaded on 11/02/2011 for the course EE 114 taught by Professor Murmann during the Fall '08 term at Stanford.

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10_Lecutre - EE114 Lecture 10 Lecture 10 Backgate Effect...

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