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12_Lecutre - EE114 Lecture 12 Lecture 12 PVT Variations...

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EE114 Lecture 12 R. Dutton, B. Murmann 1 EE114 (HO # 16) Lecture 12 PVT Variations Device Mismatch R. Dutton, B. Murmann Stanford University R. Dutton, B. Murmann 2 Re-cap What we’ve covered so far Device modeling Analysis tools (Miller approximation, ZVTC) Fundamental stage configurations (CS, CG, CD) What we have implicitly assumed We have nearly ideal current and voltage sources available to set up the transistors’ bias points Transistor parameters and supply voltage do not vary The next set of lectures will move us toward the practical implementation of transistor stages Focusing on biasing schemes that are insensitive to variations commonly seen in IC technology EE114 (HO # 16)
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EE114 Lecture 12 R. Dutton, B. Murmann 3 EE114 (HO # 16) Overview I ref ! ! V DD V DD V BIAS1 V BIAS2 Supply Independent Bias Circuit V DD P rocess, V oltage and T emperature Variations, Device mismatch (Lecture 12) Lecture 14 Current Mirrors Lecture 13 Biasing Considerations Lecture 15 R. Dutton, B. Murmann 4 EE114 (HO # 16) PVT Variations PROCESS Variations between production lots "Slow, Nominal and Fast" corners VOLTAGE – V DD is usually specified only within ± 10% E.g. V DD = 4.5…5.5 V for our technology TEMPERATURE Ambient temperature variations 0…70°C (or -40…125°C)
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EE114 Lecture 12 R. Dutton, B. Murmann 5 EE114 (HO # 16) Process Variations Parameter “Slow” “Nominal” “Fast” V t 0.65V 0.5V 0.35V μ C ox (NMOS) 40 μ A/V 2 50 μ A/V 2 60 μ A/V 2 μ C ox
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