18_Lecutre

18_Lecutre - EE114 Lecture 18 Lecture 18 Multi-Stage...

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EE114 Lecture 18 R. Dutton, B. Murmann 1 Lecture 18 Multi-Stage Amplifiers (Differential Stages) R. Dutton, B. Murmann Stanford University EE114 (HO #22) R. Dutton, B. Murmann 2 Single-Ended Cascading Problems Output quiescent point voltage (V DS ) is equal to input quiescent point (V GS ) – Usually not a good choice – Want V DS ~ V DD /2 and V GS ~ V t + a few hundred mV Hard to guarantee a stable operating point – Any error in V B1 (e.g. due to ~10mV V t mismatch in the bias generator) will be amplified by subsequent stages and may rail the output I B V B3 I B V B2 I B V B1 EE114 (HO #22)
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EE114 Lecture 18 R. Dutton, B. Murmann 3 Cascading Differential Amplifiers Does this really work (and why) Answer : YES, absolutely (and open-loop, without feedback to control node voltages) Why does it work : The current sources demand that drain currents obey; V GS values are then fixed, in turn setting drain voltages EE114 (HO #22) R. Dutton, B. Murmann 4 How much gain (and bandwidth) More gain per stage is not always best. Ultimately there is a gain- bandwidth trade-off, limited by the transistor f T . Hence, cascading multiple stages with less gain (and more bandwidth each) is one way to maximize overall gain and bandwidth. R L R L R L R L Let’s look the half-circuit with loading But: there’s no free lunch. In the end you can’t cascade to get more gain and still get bandwidth=f T . Let’s see why… EE114 (HO #22)
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EE114 Lecture 18 R. Dutton, B. Murmann 5 Cascading (Diff-Pair “in disguise”) I TAIL M1 V ip V im M2 M1 R v id v od I D =I TAIL /2 Source-Follower-CG--Gain: •High R in ; moderate/high R out •1/2 Gain of single CS * •This is single-ended output from Diff-Pair v in =v id v x v o2 Differential Mode Half Circuit
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This note was uploaded on 11/02/2011 for the course EE 114 taught by Professor Murmann during the Fall '08 term at Stanford.

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18_Lecutre - EE114 Lecture 18 Lecture 18 Multi-Stage...

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