22_Lecutre

22_Lecutre - EE 114 Lecture 22 R. Dutton, B. Murmann 1...

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Unformatted text preview: EE 114 Lecture 22 R. Dutton, B. Murmann 1 Lecture 22 Design Examples (DP 2009 and DP 2008) R. Dutton, B. Murmann Stanford University EE114 (HO #26) R. Dutton, B. Murmann 2 Pore-Based Bio-Sensor Chip (hypothetical App.) Routed to these O/As Routed to these O/As Bias Ref. Quad 3 Bias Ref. Quad 4 Bias Ref. Quad 1 Q2 Q1 Q3 Q4 Bias Ref. Quad 2 Each pore has a different diameter. This changes R PU , R PL as well as the ratio. Hence, for the array the common mode voltage range is as specified. Off-chip capacitive loading will be a problem and each amplifier needs to be able to handle that. salt water EE114 (HO #26) 2 2 1pF EE 114 Lecture 22 R. Dutton, B. Murmann 3 Input Stage gives us CMRR (I.e. other stages give CMRR=1, 0dB) Only block that gives voltage gain (two ways to consider the gain; discussed below) Output Buffer needed to drive the load (which contributes to BW but otherwise wastes power) Stages (and Roles): CMRR, Gain, Buffer EE114 (HO #26) R. Dutton, B. Murmann 4 V out (dm) V in (dm) M 1 M 2 M 3 M 4 M 5 R L R S I D1 = I TAIL /2 Differential Model Half-Circuit CS CD EE 114 Lecture 22 R. Dutton, B. Murmann 3 Input Stage gives us CMRR (I.e. other stages give CMRR=1, 0dB) Only block that gives voltage gain (two ways to consider the gain; discussed below) Output Buffer needed to drive the load (which contributes to BW but otherwise wastes power) Stages (and Roles): CMRR, Gain, Buffer EE114 (HO #26) R. Dutton, B. Murmann 4 V out (dm) V in (dm) M 1 M 2 M 3 M 4 M 5 R L R S I D1 = I TAIL /2 Differential Model Half-Circuit CS CD EE114 (HO #26) EE 114 Lecture 22 R. Dutton, B. Murmann 5 Constraints : dc--max. voltage excursion, otherwise M5 can turn off ac/transient...
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22_Lecutre - EE 114 Lecture 22 R. Dutton, B. Murmann 1...

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