29_Lecutre - Lecture 29 EE 114 Lecture 29 Technology...

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EE 114 Lecture 29 R. Dutton, B. Murmann 1 Lecture 29 Technology Scaling– Beyond EE114 MOSFETs R. Dutton, B. Murmann Stanford University EE114 (HO #33) R. Dutton, B. Murmann 2 MOS Level 1 Figures-of-Merit (FoM) Long Channel Model ds m g g Current Efficiency Transit Frequency Intrinsic Gain D m I g OV V 2 = 2 OV L V 2 3 μ = gs m C g OV V 2 ! " •Simplicity of Level 1 has allowed near-perfect accuracy in having hand-calculations and SPICE-simulations agree •What are the trends in state-of-the-art MOS technology? •What modeling and methodology is needed for advanced MOS devices? I DS = KP 2 " W L eff " V GS # V t ( ) 2 " 1 + $ V DS ( ) V t = V TO + % 2 & # V BS # 2 & ( ) EE114 (HO #33)
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EE 114 Lecture 29 R. Dutton, B. Murmann 3 1.8V 3.3V CMOS core I/O for HV interface DE core for current sources I ds ?? STI D rain- E xtended g m /g ds Trends in Scaling BSIM Different “flavors” of Transistors: Core Digital, I/O, Special Devices (we’ll come back to special devices) Two Problems : •Decrease in intrinsic gain •Bias dependent EE114 (HO #33) R. Dutton, B. Murmann 4 Dependence on V DS The long channel model predicts that g ds and g m /g ds are independent of V DS As long as device is biased in active region This is also no longer true in modern devices – g ds (and therefore g m /g ds ) shows a significant dependence on V DS V DS I D OP1 Slope = g ds1 OP2 Slope = g ds2 Physical effects beyond “channel length modulation” critical EE114 (HO #33)
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EE 114 Lecture 29 R. Dutton, B. Murmann 5 Observations – Intrinsic Gain g m/ g ds shows a strong dependence on V DS bias Mostly due to varying g ds There is a gradual transition from triode to active Long channel model would have predicted an abrupt change to large intrinsic gain at V DS = V OV Typically need V DS > V OV + 4kT/q to ensure at least moderate intrinsic gain At high V DS , g ds increases due to SCBE (substrate current induced body-effect); this causes a decrease in g m /g ds Highly technology dependent, and usually not present in PMOS devices If you are interested in more details, please refer to EE316 or a similar course EE114 (HO #33) R. Dutton, B. Murmann 6 The Good News •Large improvements in f T •Product of g m /I d times f T is becoming sharper; closer to the sub-threshold region EE114 (HO #33)
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EE 114 Lecture 29 R. Dutton, B. Murmann 7 MOS R&D Prototypes vs. Production Versions Production Prototypes: R&D Prototype Technology: Non-classical structures, physics limited, drastic variations, and higher cost Power- and robustness-constrained, adaptive, billion-scale integration, gigaHz operation 65nm (2005) 45nm (2007) 32nm (2009) 22nm (2011) 16nm (2013) 11nm (2015) 30nm (2000) 20nm (2001) 15nm (2001) 10nm (2003) 7nm (2005) 5nm (?) Source: Intel, ITRS EE114 (HO #33) R. Dutton, B. Murmann 8 Example--45 nm Technology Node -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1E-9 1E-8
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