Lecture6

Lecture6 - April 14, 2011 Page 9 V DD F(In1,In2,InN) In1...

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Welcome Tuesday, April 12, 2011 8:19 PM April 14, 2011 Page 1
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EDP/PDP Tuesday, April 12, 2011 10:21 AM April 14, 2011 Page 2
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April 14, 2011 Page 3
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April 14, 2011 Page 4
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Ring Oscillator Analysis Wednesday, April 13, 2011 10:44 PM April 14, 2011 Page 5
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Vin Vout C L Vd d I VDD (mA) 0.15 0.10 0.05 V in (V) 5.0 4.0 3.0 2.0 1.0 0.0 Short Circuit Current Tuesday, April 12, 2011 10:17 AM April 14, 2011 Page 6
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N p + p + Reverse Leakage Current + - V dd GATE I DL = J S A Vout Vd d Sub-Threshold Current Drain Junction Leakage JS = 10-100 pA/ m2 at 25 deg C for 0.25 m CMOS JS doubles for every 9 deg C! Static (Leakage) Power Tuesday, April 12, 2011 10:19 AM
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Unformatted text preview: April 14, 2011 Page 9 V DD F(In1,In2,InN) In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only High noise margins : V OH and V OL are at V DD and GND , respectively. No static power consumption : There never exists a direct path between V DD and V SS ( GND ) in steady-state mode. Comparable rise and fall times: (under appropriate sizing conditions) Combinational Gates Wednesday, April 13, 2011 10:48 PM April 14, 2011 Page 10 April 14, 2011 Page 11 DeMorgan's Theorem Thursday, April 14, 2011 10:52 AM April 14, 2011 Page 12 April 14, 2011 Page 13...
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This note was uploaded on 11/02/2011 for the course ECE 165 taught by Professor Staff during the Spring '08 term at UCSD.

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Lecture6 - April 14, 2011 Page 9 V DD F(In1,In2,InN) In1...

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