Lecture7

Lecture7 - Welcome Thursday,April14,2011 12:31PM...

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Talk about sizing for Problem 1 in Lab What do I mean by 200 times the capacitance? Error at the end of last lecture. Midterm next Thursday 4/28 Welcome Thursday, April 14, 2011 12:31 PM April 19,2011 Page 1
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D A BC D A B C 1 2 22 4 4 8 8 6 3 6 6 OUT = D + A • (B + C) D A D A B C Sizing Gates Wednesday, April 13, 2011 10:49 PM April 19,2011 Page 6
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Switch Delay Model A R eq A R p A R n C L A C L B R n A R p B R p A R n C int B R p A R p A R n B R n C L C int NAND2 INV NOR2 Delay Models Wednesday, April 13, 2011 10:49 PM April 19,2011 Page 7
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V DD V DD 0 PDN 0 V DD C L C L PUN V DD 0 V DD -V Tn C L V DD V DD V DD |V Tp | C L S DS D V GS S S D D V GS Sources of Delay Dependence Wednesday, April 13, 2011 10:51 PM April 19,2011 Page 10
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Wednesday, April 13, 2011 11:04 PM April 19,2011 Page 11
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-0.5 0 0.5 1 1.5 2 2.5 3 0 100 200 300 400 A=B=1 0 A=1, B=1 0 A=1 0, B=1 time [ps] Voltage [V] Input Data Pattern Delay (psec) A=B=0 16 7 A=1, B=0 4 A= 0 1, B=1 61 A=B=1
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Lecture7 - Welcome Thursday,April14,2011 12:31PM...

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