Lecture15

Lecture15 - Welcome Thursday,May19,2011 10:06AM Forproject:...

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Adder stage 1 Wiring Adder stage 2 Wiring Adder stage 3 Bit slice 0 Bit slice 2 Bit slice 1 Bit slice 63 Sum Select Shifter Multiplexers Loopback Bus From register files / Cache / Bypass To register files / Cache For project: Please read Chapter 12 of Digital Integrated C ircuits Itanium 6 64 bit datapath Welcome Thursday, May 19, 2011 10:06 AM May 19, 2011 Page 1
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Improved Latches Thursday, May 19, 2011 10:35 AM May 19, 2011 Page 2
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Flip-flops 2-Phase Latches Pulsed Latches Flip-Flops Flop Latch clk 1 2 p clk clk p p 1 1 2 2-Phase Transparent Latches Pulsed Latches Combinational Logic Combinational Logic Combinational Logic Combinational Logic T c T c /2 t nonoverlap t nonoverlap t pw Half-Cycle 1 Half-Cycle 1 Pipelining Thursday, May 19, 2011 10:20 AM May 19, 2011 Page 6
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Lecture15 - Welcome Thursday,May19,2011 10:06AM Forproject:...

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