ENB240-T1-S1-2007

ENB240-T1-S1-2007 - GUT Surname Given Name/s III-III-...

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Unformatted text preview: GUT Surname Given Name/s III-III- Examination Paper SEMESTER: FIRST SEMESTER EXAMINATIONS 2007 UNIT: ENBZ40 INTRODUCTION TO ELECTRONICS — THEORY 1 DURATION OF EXAMINATION: PERUSAL: 10 MINUTES WORKING: 2 1/2 HOURS EXAMINATION MATERIAL SUPPLIED BY THE UNIVERSITY: EXAMINATION BOOKLETS — TWO (2) PER STUDENT GRAPH PAPER MM — ONE (1) PER STUDENT EXAMINATION MATERIAL SUPPLIED BY THE STUDENT: WRITING IMPLEMENTS CALCULATORS - NON PROGRAMMABLE INSTRUCTIONS TO STUDENTS: Students are prohibited from having mobile phones or any other device capable of communicating information (either verbal or written) in their possession during the examination NOTES MAY BE MADE QNLX ON THE EXAMINATION PAPER DURING PERUSAL TIME THREE (3) QUESTIONS ONLY ARE TO BE ATTEMPTED ATTEMPT EACH SECTION IN A SEPARATE EXAMINATION BOOKLET ALL QUESTIONS ARE OF EQUAL VALUE Queensland University of Technology GUT GUT Gardens Point Carseldine SECTION A (please write in separate booklet) QUESTION 1 (a) Describe the generation and recombination of hole-electron pairs in intrinsic silicon at normal room temperatures. (ni : 1.5X1010 cm" at 25 CC) (2 marks) (b) With the aid of a diagram, Show how drift currents flow in pure silicon when a voltage is applied to the material. Hence determine the resistance of a 1mm cube of silicon at a temperature of 25°C. (un=1500, up=480 cmZ/V—sec, ie. cm/sec per V/cm) (3 marks) (c) Describe how doping can alter the majority and minority carrier concentrations in p-type extrinsic silicon, and thus increase its conductivity. (2 marks) (d) Describe how the depletion region is formed in a PN junction at equilibrium. Sketch the profile of carrier concentrations in the junction. Determine the majority and minority carrier concentrations, and potential barrier (Vb) at normal room tem eratures if the doping levels in the n and p type materials are NA = 5x10 5 cm‘3, ND = 4X1016 cm' , and hi = 1.5xlO1 cm”. (IVb Vb 7’1 P o — "0 = ——p = e H = 625"” , at 25°C npO pnO (5 marks) (6) Explain how a PN junction operates to conduct when it is forward biased, and block currents when it is reverse biased. (3 marks) (t) Determine the reverse saturation current for the diode shown below, given that a voltage Vs = 15V produces a diode current ID = 14.3mA. Hence sketch a graph of ID against VD, plotting points for VD = 0.5, 0.6, 0.65, 0.7 and 0.75V. Draw a load line on the graph to determine the new values of ID and VD when V3 is reduced to 10V. Diode Eguation (modified) qVD/v q VD / ID =IS(e 77” —1),~v [Se I/UkT where , I S = Reverse Saturation Current 7] = 1.5 Thermal voltage, kT/q = 25mV at 25°C (5 marks) ENB24OT1.071 cont/. .. Ix.) QUESTION 2 (a) Describe with the aid of sketched waveforms how the rectifier circuit shown below operates to convert AC to DC. Suppr Voltage Vs]: V53= 18 Volts rms RL=1 5 Frequency SOHZ AC Diode Conduction Voltage N Assume VD = 1 Volt 0 Diode Conduction Angle 6Com = 30 degrees , Transfomler when RL 2 ohms (4 marks) (b) Analyse the power supply of (a) to determine: (i) Peak output voltage Vopk (ii) Peak to peak output ripple voltage (iii) Value of capacitor C (iv) Average and maximum value of load current IL (v) Average and maximum value of diode current -t/ (Note: Vpk = VrmS\/2 , Capacitor Discharge Equation, VG = V 3 /CR) (6 marks) (c) Sketch waveforms of IL, 1131 and ID; for the circuit of (a). (2 marks) ((1) Sketch a graph of V0 against Vs for the circuit shown below, and explain how it operates to stabilise the output voltage Vo when the supply Vs changes. IC Zener Characteristic Vz = 6.8 V 12 = Q Transistor Characteristics VBE = 0.7V B = 100 $=OQ Determine the following: (i) Output Voltage when Vs = 20V (ii) Line Regulation, AVo/AVS, when Vs = 20V ' (iii) Load Regulation (ie, Output Impedence = —AVo/AIL)_, when Vs = 20V. (8 marks) ENB240T1.071 cont/. .. SECTION B (please write in separate booklet) QUESTION 3 (a) Sketch the carrier concentrations in a base region of a forward biased NPN transistor and explain how the collector current is controlled by the base-emitter voltage. Assume that the minority carrier concentration at the emitter edge of the active base region is raised by a factor (flies/r“ e “(T when a forward bras base—emitter voltage 15 applied. (3 marks) (b) Hence use a similar sketch to explain the meaning of the incremental emitter resistance r8 = AVbe/Ale , and derive an equation for its value at a bias current IE. (2 marks) (c) Explain why both the emitter and collector currents also vary slightly with the collector voltage, and sketch a graph of Ic against Vce for a forward biased transistor in which Vbe is constant. (3 marks) (d) Determine the quiescent conditions IB, Ic, Vc, and VE of the transistor amplifier shown below when Vcc = 15Volts. Transistor Parameters VBE = 0.66 B =11FE = rb/ = 0 ohms rC = 00 Rin Rout (i) Describe how the emitter resistance RE can be considered to be included inside the transistor itself, and how it effects the parameters of the resultant transistor. (ii) Assuming that Vcc is at a voltage such that Ic = 5.5mA, draw the small signal equivalent circuit, and hence determine: Voltage Gain, AV = AVout/AVin ,when R5 = 0, and RL = 00 Input Resistance, Rm. Output Resistance, Rout. (iii) Deteimine the approx. value of capacitor C1 to obtain a low frequency cut—off frequency of 500 Hz. (12 marks) ENB240T1.071 cont/. .. QUESTION 4 (a) Describe the characteristics of a emitter follower stage and explain why they are often used at the output of multistage transistor amplifiers. (2 marks) (b) Describe the principle of operation of an n-channel JFET transistor and sketch both its transfer and output characteristics. (4 marks) (c) Consider the 2-stage JFET input amplifier shown below. JFET [T12 Parameters IDSS = 32H'IA l Vp | = 2V rds‘C’O Transistor (T2 1 Parameters VBE = [3 = 100 Ziu 0V Zoutl Zinl Zout Common Source Amp Emitter Follower )2 (i) Determine the following: o Bias conditions of FETI (ID, Vg, Vs). (Note: T2 does not affect ID) - Transconductance (gIn ) of the FET at the bias conditions. - Bias conditions of T2 ( IE, 13, VB=VD) to produce an output bias Voltage (VE=V0m) of 1 OVolts. 0 Value of RD to produce the output bias Voltage (VE =Vout) of lOVolts. VGs V Assume ID =IDSS {1— p (ii) Draw the small signal equivalent circuit of the amplifier T1 and hence determine: Its open circuit Voltage gain (ie. AVD/AVin when T2 is disconnected). Input Impedance (Zin = Zinl). Output Impedance (Zoutl). (iii) Draw a simplified small signal model of the complete amplifier (T1 and T2) and hence determine: Overall Voltage Gain (AVom/AVin). Output Impedance Zout ...... ..(14 marks) END OF PAPER ENB24OT1.071 ...
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ENB240-T1-S1-2007 - GUT Surname Given Name/s III-III-...

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