This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: GUT Given Name/s Surname IIII.. SEMESTER: Examination Paper FIRST SEMESTER EXAMINATIONS 2010 UNIT: ENBZ4O INTRODUCTION TO ELECTRONICS  THEORY 1 DURATION OF EXAMINATION: PERUSAL: 15 MINUTES
WORKING: 3HOURS EXAMINATION MATERIAL SUPPLIED BY THE UNIVERSITY: EXAMINATION BOOKLETS  TWO (2) PER STUDENT
GRAPH PAPER MM  ONE (1) PER STUDENT EXAMINATION MATERIAL SUPPLIED BY THE STUDENT: WRITING IMPLEMENTS
CALCULATORS  NON PROGRAMMABLE INSTRUCTIONS TO STUDENTS: Students are prohibited from having mobile phones or any other device capable of communicating information
(either verbal or written) in their possession during the examination NOTES MAY BE MADE QNLX ON THE EXAMINATION PAPER DURING PERUSAL TIME THREE (3) QUESTIONS ONLY ARE TO BE ATTEMPTED SECTION A  SE TI N B  THREE (3) QUESTIONS ONLY ARE TO BE ATTEMPTED ATTEMPT EACH SECTION IN A SEPARATE EXAMINATION BOOKLET ALL QUESTIONS ARE OF EQUAL VALUE Queensland University of Technology GUT GUT Gardens Point Kelvin Grove VI 1
SECTION A (ANALOG) Answer 3 out of the 4 questions in this section QUESTION 1 (21) Describe, with the use of an energy level diagram, how doping can be used to increase the
number of carriers available to conduct current in Ntype silicon. Determine the carrier concentrations in extrinsic silicon with a doping density ND = 2x1016/cm3,
assuming n, zl.5x1010/cm3 .
.... ..(5 marks) (b) Describe with the aid of a diagrams, how the depletion region and potential barrier are
formed at a PN junction, with no applied voltage. Determine the majority and minority carrier concentrations, and potential barrier (Vb), at normal
room temperatures, if the doping levels in the n and p type materials are: N A = 6x1015/cm3, N9 =
2x1016/cm3, and ti, = 1.5x1010/cm3. ' qu Vb nn" ppo 67T =625mV, at 25°C ..... ..(5 marks) (c) Describe with the aid of waveforms how the rectiﬁer circuit shown below operates to convert
AC to DC. ID IL In ut Su 1 Volta e
Vs = 18 Volts peak AC RL Frequency 50Hz
V C
’\1 s 100 V0 Diode Conduction Voltage Assume VD = 1 Volt
0V Determine the output ripple voltage and the value of capacitor C for a diode conduction angle of
20 degrees.
—t
Capacitor Discharge Equation, Vc = Ve CR Estimate the average and peak diode currents. 
.... ..(10 marks) ENB240T1.101 c0nt/. .. QUESTION 2 (a) Sketch simple circuits, and describe the main features (ie. Voltage gain, Current gain, Input Impedance, Output Impedance) of Common—Base, CommonEmitter, and CommonCollector
transistor ampliﬁers. ...... ..(5 marks) (b) Determine the quiescent conditions 13, IC, VC, and of the transistor ampliﬁer shown below
when Vcc = 15Volts. Vcc Transistor Parameters VBE = 0.6 B = hFE = 200
rb/ = 0 ohms
rc = 00 Assuming that Vcc in the above ampliﬁer is adjusted (if necessary) to a level such that Ic =
5mA, draw the small signal equivalent circuit, and hence determine: (i) Voltage Gain, A = AVoutt/AVin, when R5 = 0, and RL = 00.
(ii) Input Impedance, Zin.
(iii) Output Impedance, Zout. .... ..(11 marks) (c) Use the simpliﬁed midfrequency ac model of the ampliﬁer, shown in the dotted box below, to determine the overall voltage gain Vout/Vs of the ampliﬁer in (b) when R3 = 500 ohms and
RL = 5k ohms. Rs=500 ENB240T1.101 cont/. .. QUESTION 3 (3) Brieﬂy descibe the principle of operation of an nchannel JFET, and sketch both its transfer
and output characteristics. .... ..(6 marks)
(b) Consider the FET ampliﬁer shown below.
VCC = 12V JFET Parameters
1055 = l Vp l = 4V
rds = 00
Assume
Drain Current,
2
V
ID = IDSS [1— ﬂ]
VP
(i) Determine:
Bias conditions (19, V0, V5, VD).
Transconductance (gm ) of the FET at the bias conditions.
(ii) Draw the small signal equivalent circuit of the ampliﬁer, and hence determine:
Small signal Voltage Gain
Output Impedance, Zout.
.....(10 marks) (c) Show how you would use an emitter follower to reduce the output impedance of the above
ampliﬁer, and hence estimate the new Zout if the emitter follower has the following characteristics (B = 100, rb’ = 0, rc = 1 ohm)
..... ..(4 marks) ENB240Tl .101 cont/. .. QUESTION 4
(a) Explain how the differential ampliﬁer shown below operates to amplify differential input
signals, and reduce the amplitude of any commonmode input. Vcc = 12V .....(4 marks) (b) Determine the bias conditions ( 13, IC, VE,VO) for the differential amplifier shown below,
assuming that the input bias conditions are V1 = V2 = OVolts. Vcc =+15V Assume
VBEQ = hfe = B = 200 rb =00hms
rc =00 VEEZ 15V Use small signal equivalent circuits to determine:
(i) Differential voltage gain. (ii) Commonmode voltage gain. “.02 marks) (c) Show how you could replace R5 in the above circuit with a constant current sink (using an additional resistor and 2 transistors), and describe how this would improve the differential
ampliﬁer. .....(4 marks) ENB240T1.101 cont/. .. SECTION B (DIGITAL)
Use a separate booklet for this section Answer 3 out of the 4 questions in this section QUESTION 5 ( Do not use a calculator, and show ALL working)
(:1) Determine the decimal equivalent of the following numbers (i) (10110110); (ii) (01001.11)2 ..... ..(3 marks)
(b) Represent the decimal number 157.375 in:
(i) Binary
(ii) Hex
(iii) IEEE Floating Point
..... ..(7 marks) (c) Explain what is meant by the complement of a number, and hence how subtraction can be
done with an adder, when neg numbers are represented in complement form. Hence represent the negative decimal number ~73 in 2’s complement form, assuming 8bits.
..... ..(3 marks) ((1) Represent the hex number (5E)16 as an array of 2 ASCII chars.
(Note: ‘0’ = (30)16, ‘A’ = (41)16)
..... ..(2 marks) (e) Use the basic rules of binary addition to derive the circuit diagram of a half adder with sum and carry outputs, using exclusive OR gates. Show how a 2 of these half adders can be used to
make a full adder. ..... ..(5 marks)
QUESTION 6
(a) Express the following function as a sum of minterms.
Z 2 A (B C) + A (B + C) ..... ..(3 marks) (b) A Boolean function Z is dependant upon 3 inputs (ABC) and given as a sum of minterms:
Z (A,B,C) = 2 m (0,2,4,5,6) Plot Z on a Karnaugh map and express Z as:
(i) a minimum sum
(ii) a minimum product
..... ..(5 marks) (c) Design a 3bit counter, using D ﬂipﬂops, that can count up in the following sequence
ABC 2 000 > 100 .010 > 001 >011>111
Once the counter reaches 111 it is to remain there until it is cleared asynchronously with a Reset
input R.
.....(12 marks) ENB240T1.101 cont/. .. QUESTION 7 (a) An asynchronous machine has 2 inputs (A,B) and one output Z.
The output Z is to be true when AB = 11, provided that the previous value of AB 00 was 10.
Draw a model of the system together with a suitable state assignment and the output equation. ..... ..(4 marks) (b) Implement the asynchronous model shown below assuming that only 1 input can change at a
time. _ _ Z] AB+A§+XB 22 State ASSIgnment
’AE AB+AB i Next State Note: Do NOT draw the circuit, just produce the minimised equations.
..... ..(7 marks) (c) A synchronous machine has an input X and an output Z.
The output Z is to be 2 clock pulses wide every time X goes true. Draw a model of this synchronous machine together with a suitable state assignment, and
output equation, assuming that the input X is very slow compared to the clock. Draw a transition table for this synchronous system and implement it using J K ﬂipﬂops. Note: Do NOT draw the circuit, just produce the minimised equations.
..... ..(9 marks) ENB240T1 . 101 cont/. .. QUESTION 8 (a) Brieﬂy describe the internal structure of programmable logic devices such as a GAL20V8
(i) Combinational Logic
(ii) Asynchronous Sequential Logic
(iii) Synchronous Sequential Logic
..... ..(6 marks) (b) A 7segment decoder is required to decode a 3bit binary input (ABC) and display the result
E,l ,2,3,4,5,6, or F as appropriate on a 7segment display as indicated below. 7Segment Display Encoder Note: A = Most Signiﬁcant Bit, E = Empty (ABC=000), F = Full (ABC = 111) Draw the truth table, and show how you would use WINCUPL to design the system using a
GAL20V8. (Note: you can use the TABLE feature in WINCUPL, if you wish)
..... ..(7 marks) (c) Design a 3bit resettable, Up/Down, Binary counter (with stops), using a GAL20V8.
The counter has an Up input (1=Up, O=Down) and a synchronous Reset input (R), as indicated
in the diagram below. U=Up o A B,C = Counter Up/Down
Counter
> (GALZOV) R=Reset E= Empty
F = Full Clock 0 If the R input is true when the clock goes high the Counter is to return to 000.
The Counter is to have an Empty output (ABC = 000) and a Full output (ABC=11 l). The counter is to stop counting up once it is Full, and stop counting down when it reaches Empty (Note: you can use the SEQUENCED feature in WINCUPL if you wish)
...... ..(7 marks) END OF PAPER ENB240T1.101 ...
View
Full Document
 Three '10
 MCGREGOR
 The Circuit

Click to edit the document details