ENB240-T2-S1-2007

ENB240-T2-S1-2007 - Student Number Surname Given Name/s...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 2
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 4
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Student Number Surname Given Name/s III-III. _ Examination Paper SEMESTER: FIRST SEMESTER EXAMINATIONS 2007 UNIT: ENB24O INTRODUCTION TO ELECTRONICS - THEORY 2 DURATION OF EXAMINATION: PERUSAL: 10 MINUTES WORKING: 2 1/2 HOURS EXAMINATION MATERIAL SUPPLIED BY THE UNIVERSITY: EXAMINATION BOOKLETS EXAMINATION MATERIAL SUPPLIED BY THE STUDENT: NIL, EXCEPT FOR WRITING IMPLEMENTS INSTRUCTIONS TO STUDENTS: Students are prohibited from having mobile phones or any other device capable of communicating information (either verbal or written) in their possession during the examination NOTES MAY BE MADE QNLX ON THE EXAMINATION PAPER DURING PERUSAL TIME THREE (3) QUESTIONS ONLY ARE TO BE ATTEMPTED ALL QUESTIONS ARE OF EQUAL VALUE Queensland University of Technology Gardens Point GUI Kelvin Grove W Carseldine Caboolture QUESTlON 1 (a) Convert the following decimal number to 8-bit signed binary ( ie. 2’s complement) and equivalent hex (i) 71 (ii) —87 ...... ..(2 marks) (b) Represent the decimal number 72.3125 in (i) Binary (ii) Hex (iii) BCD (iv) IEE Floating Point ...... ..(6 marks) (c) In order to increase the range of 8-bit signed binary numbers, it has been decided to represent them in the following format. I 2-bit exponent (e) 6—bit binary number (n) l N = 26 X n Represent the decimal numbers 19 and 320 in this format . What is the range of numbers that can be represented, and the resolutions at the top and bottom ends of the scale? (Note: the resolution at any point is the difference between a valid number and its neighbour) ...... ..(5 marks) (d) Perform the following arithmetic operation showing all carries and borrows (i) (110101)2 + (11001)2 (ii) (11011101); - (1100111)2 (iii) (1011)2 x (1010); ...... ..(5 marks) (e) Explain how subtraction can be preformed in an adder when signed binary numbers are represented in 2,5 complement ...... ..(2 marks) ENB24OT2.071 ( .... . .contdl) QUESTION 2 (a) Draw a circuit diagram to implement the following boolean function without any minimisation. —— . Z = (A + AC).(AB + C) Now simplify the function using boolean algebra, and produce a simplified circuit. ...... ..(5 marks) (b) A boolean function Z is given by Z (A,B,C,D) = Z m (O,1,2,3,5,7,8,10,15) Plot Z on a Karnaugh map and express Z as: (i) a fundamental sum (ii) a minimum sum (iii) a fundamental product (iv) a minimum product. ...... ..(4 marks) ((3) Design an economical circuit that will convert a 4-bit binary input (ABCD) to a 5-bit BCD output (T PQRS) where T has a weight of ten and PQRS have weights 8421, using only Nand gates and inverters, if necessary. ...... ..(5 marks) (d) Draw the circuit diagram of a full adder with sum, carry—generate and carry propagate outputs, and explain how this device can be use to reduce the execution time of multiple bit adders. ...... ..(6 marks) UESTION 3 (a) Design a modulo-6 Up/Down binary counter to count in binary over the range ABC = 000 to 101 using JK flip-flops, ensuring that the counter can escape out of the redundant states. The counter is to have an output Z when it is in state 101 = 5 ...... ..(12 marks) (b) Draw a circuit of a 4 stage (ABCD) Johnson counter ( twisted ring) using D flip-flops and explain how it operates. Describe any advantages and disadvantages it may have compared with a 4—stage binary counter. ...... ..(3 marks) ENB24OT2.071 ( .... ..contd/) DJ (c) Show how you would implement the following repetitive sequence of pulse trains (Pl .P2,P3,P4) using the 4 stage (ABCD) Johnson counter of part (b). T1 T2 T3 T4 T5 T6 T7 T8 T1 T2 T3 1 l I l l l l l | | l l P1__l—L____._J—L P2 _____J—_—L___l—_ P3 l l 1 P4 | ...... ..(5 marks ) UESTION 4 (a) An asynchronous sequential circuit has 2 inputs (AB) and two outputs (P,Q). Starting from the condition where all inputs and outputs are false, the ouput P is to be true whenever A and B are both true provided that A went true before B. The output Q is to go true when A and B provided that B went true before A. Both outputs are to be cleared when A and B go false. Draw a model of the system, suitably define the states, and produce the output equations. ...... ..(4 marks ) (b) Implement the asynchronous model shown below using Nand Gates assuming that only 1 input can change at a time. State Assignment ...... ..(8 marks ) (0) Draw a model of a synchronous machine that will produce an output Z of width 1 clock pulse every time an input X goes true for at least 2 clock pulses, and show how you would implement it using D type flip flops. ' ...... ..(8 marks ) END OF PAPER ENB24OT2.071 ...
View Full Document

This note was uploaded on 11/03/2011 for the course EN 40 taught by Professor Mcgregor during the Three '10 term at Queensland Tech.

Page1 / 4

ENB240-T2-S1-2007 - Student Number Surname Given Name/s...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online