ENB244-T1-S2-2008

ENB244-T1-S2-2008 - GUT Surname Given Namels III-I...

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Unformatted text preview: GUT Surname Given Namels III-I..- Examination Paper SEMESTER: SECOND SEMESTER EXAMINATIONS 2008 UNIT: ENBZ44 MICROPROCESSORS AND DIGITAL SYSTEMS - THEORY 1 DURATION OF EXAMINATION: PERUSAL: 10 MINUTES WORKING: 2 HOURS EXAMINATION MATERIAL SUPPLIED BY THE UNIVERSITY: EXAMINATION BOOKLETS EXAMINATION MATERIAL SUPPLIED BY THE STUDENT: NIL, EXCEPT FOR WRITING IMPLEMENTS INSTRUCTIONS TO STUDENTS: Students are prohibited from having mobile phones or any other device capable of communicating information (either verbal or written) in their possession during the examination NOTES MAY BE MADE QNLI ON THE EXAMINATION PAPER DURING PERUSAL TIME THREE (3) QUESTIONS ONLY ARE TO BE ATTEMPTED ALL QUESTIONS ARE OF EQUAL VALUE Queensland University of Technology GUT GUT GUT Gardens Point Kelvin Grove Carseldine QUESTION 1 (a) What are the main advantages and disadvantages of implementing digital systems with PLD’s instead of microprocessors. ......... .. (3 marks) (b) Briefly describe the internal structure of programmable logic devices such as a GALZOVS and explain how they can be used to implement: (i) Combinational Logic (ii) Asynchronous Sequential Logic (iii) Synchronous Sequential Logic ......... .. (5 marks) (C) A 7-segment translator is required to display the state of an industrial machine on a common cathode 7-segment display as shown below. 7—Segment Display Industrial Machine 0V The encoder has 4 inputs (P,Q,R,S), and produces 7 outputs (abcdefg) to drive the segments of the display. One of the characters (1, 2, 3, E, 0) is displayed, depending upon the state of the machine. The display is to show 0 when no inputs are active. Use a truth table to obtain the logic equations for 7—Seg Translator, and implement it using WinCUPL and a GAL20V8 (no need to minimise the equations, unless there are too many terms) ......... .. (12 marks) ENB244T1.082 (cont/....) QUESTION 2 (a) Simple PLD devices such as GAL’s have a single block of n macrocells (a block of 8 in the case of a GAL20V8) with predefined pinouts. Explain why devices such as the Altera Max7128 are called complex PLD’s, and describe their main features. ........ .. (5 marks) (b) Use Altera AHDL to design a 3—bit Gray to Binary decoder, as indicated in the diagram below. Ignore the OE line at this point. 3-bit Gray Code Q Gray to Binary B DECODER R (Max7128) Binary Output C ---——- OE Gray Code PQR 2 000, 001, 011, 010, 110, 111, 101, 100, 000.... ........ .. (5 marks) (0) Show how you would modify the above decoder so that the outputs A, B, and C are tristate, with an Output Enable input OE. ........ .. (2 marks) ((1) Use Altera AHDL to design a 3-stage (i.e. 3 flip—flops, A,B,C) Johnson (Twisted Ring) Counter with decoded outputs (Load, Processing, Unload) as indicated below. Waveforms Clock 0 1 2 3 4 5 0 1 2 3 Basic 1 Counter B I l l Outputs C I l I I T _l_|____l—|__— Decoded 0 Load I Load Outputs T1234 I Processing I Processing T5 lnloadl ........ .. (8 marks) ENB244T1.082 (cont/ . . ..) QUESTION 3 (a) Show how you would define an entity in VHDL with: o 2 Boolean inputs (a,b). 4 Input bits X that are to be grouped together. 2 Output bits (c, d) that are also fed back into the inputs of the system. 4 Output bits Z that are to be grouped together. 2 Tristate Outputs (e,i). ........ ..( 4 marks) (b) A block diagram of a 2-bit digital comparator is shown below. x0 X1 —-——> 2-bit Digital COMPARATOR EQ Y0 ——> (Max7128) LT Draw the truth table of the comparator. Produce GT, EQ, and LT output equations, and use the equations to implement the Comparator in VHDL. ........ ..( 6 marks) (0) Use the PROCESS statement in VHDL to implement a 5-bit Arithmetic Shift Right Register with parallel load as indicated in the block diagram below. DataIn(4..0) 5-bit Load ARITHMETIC SHIFT RIGHT Q DataOut(4~0) Clock REGISTER Note: An arithmetic shift right is one in which the most significant bit (i.e. the sign bit) remains unchanged by the shift right (ie 01100 -> 00110, 10110 -> 11011). ........ ..( 10 marks) ENB244T1.082 (cont/.. ..) QUESTION 4 (a) Use either AHDL or VHDL to implement a 4-bit Up/Down binary counter using a behavioural model (ie. telling the compiler what you want the counter to do, and letting the compiler do the work). The counter is to also have the following outputs. Zero is to be true when the counter I 0. Full is to be true when the count I 15. Carry is to be true when the count is equal to 15 and counting UP, and also when the count is at 0 and counting DOWN. .... .;....( 6 marks) (b) Draw a graphical model of a synchronous state machine that will produce an output pulse Z, of width 2 clock pulses, every time the input X goes from 0 to 1. Show how you would implement the model in either AHDL or VHDL. ........ ..( 7 marks) (c) Draw a model of an asynchronous (i.e. no clock) Winner Detector for 2 inputs A and B, and show how you would implement it in either AHDL or VHDL. ........ ..( 7 marks) END OF PAPER ENB244T1 .082 ...
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This note was uploaded on 11/03/2011 for the course EN 40 taught by Professor Mcgregor during the Three '10 term at Queensland Tech.

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ENB244-T1-S2-2008 - GUT Surname Given Namels III-I...

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