ENB244-T1-S2-2009

ENB244-T1-S2-2009 - Surname Given Name/s III-III-...

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Unformatted text preview: Surname Given Name/s III-III- Examination Paper SEMESTER: SECOND SEMESTER EXAMINATIONS 2009 UNIT: ENBZ44 MICROPROCESSORS AND DIGITAL SYSTEMS - THEORY 1 DURATION OF EXAMINATION: PERUSAL: 10 MINUTES WORKING: 2 HOURS EXAMINATION MATERIAL SUPPLIED BY THE UNIVERSITY: EXAMINATION BOOKLETS EXAMINATION MATERIAL SUPPLIED BY THE STUDENT: NIL, EXCEPT FOR WRITING IMPLEMENTS INSTRUCTIONS TO STUDENTS: Students are prohibited from having mobile phones or any other device capable of communicating information (either verbal or written) in their possession during the examination NOTES MAY BE MADE QNLI ON THE EXAMINATION PAPER DURING PERUSAL TIME THREE (3) QUESTIONS ONLY ARE TO BE ATTEMPTED ALL QUESTIONS ARE OF EQUAL VALUE Queensland University of Technology 6101' GUT Gardens Point Kelvin Grove QUESTION 1 (a) Some digital systems (or subsystems) are implemented with microcontrollers, while others are implemented in PLDs. What are the main advantages and disadvantages of the PLD type implementations compared with microcontrollers? ......... .. ( 3 marks) (b) Briefly describe the main differences between the following types of PLDs, giving at least one example of their appropriate usage. (i) GALs such as the GAL20V8 (ii) CPLDs such as the MAX7128 (iii) FPGAs such as the Cyclone II (2C3 5) ......... .. ( 7 marks) (c) A 7-segment decoder is required to display the state of an industrial machine on a common cathode 7-segment display as shown below. 7-Segment Display Industrial Machine 7-Seg Dec opder 0V The encoder has 4 inputs 2 (i) P,Q is a binary number that represents the machines cycle of operation (0, 1, 2, 3) as it moves through the production process. (ii) R is a fault input that is activated by the machine when it detects a fault, and is to cause the display to flash ON and OFF at a frequency of 1H2. For example, if the machine detected a fault while it was in phase 2 of its operation, the number 2 currently being displayed, would start to flash ON and OFF. (iii) S is 1 Hz clock that is used to turn the display ON and OFF under fault conditions. Produce the logic equations for the 7-Seg Decoder, and implement it using WinCUPL and a GAL20V8 (no need to minimise the equations, unless there are too many terms) ......... .. (10 marks) ENB244T1.092 (cont/. . . .) QUESTION 2 (a) A digital system is required to have a 3 digit display (7—segment, common cathode). Draw a block diagram of the display system using a multiplexed display technique. Describe the segment and digit drive outputs required to drive the display. Choose an appropriate LiteNextDigitFrequency, and explain how the system would operate to display the 3-digit number, contained in 3 Binary Coded Decimal registers (BCDl, BCD2, BCD3) within the machine. ( Assume the system has a 4-bit binary to 7-segment decoder) ........ .. ( 7 marks) (b) Use Altera AHDL to design a 4- input Data Selector with a tristate output as indicated below. 4-Input Data Selector Z Data Inputs Selected Output (MUX) s1 so OE COW> H._/ Select Inputs Explain the function of the OE input and its control of the tristate output ........ .. ( 7 marks) (c) Design a 2-stage (i.e. 2 flip-flops A,B) counter to count in the sequence AB = 00,10,11,01 with reset input R and decoded output Z = (AB=01). Derive the control equations assuming the use of D type flip flops, and implement the system using Altera AHDL. Clk Reset, (R) ........ .. ( 6 marks) ENB244T1.092 (cont/. . ..) QUESTION 3 (a) Show how you would define an entity in VHDL with: o 3 Boolean inputs (a, b, c). 2 Input bits X that are to be grouped together. 2 Output bits (6, f) that are also fed back into the inputs of the system. 4 Output bits Z that are to be grouped together. 2 Tristate Outputs (g,h). ........ ..( 4 marks) (b) Use VHDL to design the 2—bit gated binary decoder shown below 2-bit Bin to Decimal Dec Outputs DECOD ER (active low) The decoded outputs only become active when glg—2= 10 ........ ..( 7 marks) (0) Use VHDL to design a 3-stage (i.e. 3 flip-flops, A,B,C) Johnson (Twisted-Ring) Counter with decoded outputs (Load, Processing, Unload) as indicated below. 3— Stage (ABC) Load Johnson Counter Re set —'> Processing Clock UnLoad Waveforms Clock 1 2 3 4 5 6 1 2 3 4 A I | I Basic l—l 5 Counter B Outputs C I I T l I Load | Dec 0d ed 1 2 Load Outputs T234 Processing - Processing T56 Unload -.I.-- — '> Repeat ........ .. ( 9 marks) ENB244T1.092 (c0nt/. . ..) QUESTION 4 (a) Use either AHDL or VHDL to implement a 6-bit Up/Down binary counter (with stops) using a behavioural model (ie. telling the compiler what you want the counter to do, and letting the compiler do the work). Upper Stop = 50 = (110010), count when counting UP. Lower Stop = 0 = (000000), when counting Down 6-bit Binary Counter (with Stops 0, 50) zero F1111 Reset clears the counter asynchronously to 0 The counter is to also have the following outputs. Zero is to be true when the counter = 0. Full is to be true when the count = 50. ........ ..( 6 marks) (b) A state machine is required to determine when a positive going pulse X has come and gone, after the system has been reset as indicated below. Reset Finished X Detector Draw suitable models that could be used to implement the detector as: (i) A synchronous sequential circuit (requiring an additional clock input). (ii) An asynchronous sequential circuit (no clock required) (NOTE: No need to implement the circuits) Determine appropriate state assignments in each case, and state any advantages that asynchronous might have over synchronous. ........ ..( 7 marks) (c) Implement the clocked synchronous model shown below in either AHDL or VHDL, using the state machine design system that is available. Z1 _ _ 22 State Ass1gnment AB+AB+AB END OF PAPER ENB244T1.092 ...
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This note was uploaded on 11/03/2011 for the course EN 40 taught by Professor Mcgregor during the Three '10 term at Queensland Tech.

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ENB244-T1-S2-2009 - Surname Given Name/s III-III-...

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