ENB244-T1-S2-2010

ENB244-T1-S2-2010 - Surname Given Name/s III-III-...

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Unformatted text preview: Surname Given Name/s III-III- Examination Paper SEMESTER: SECOND SEMESTER EXAMINATIONS 2010 UNIT: ENBZ44 MICROPROCESSORS AND DIGITAL SYSTEMS - THEORY 1 DURATION OF EXAMINATION: PERUSAL: 10 MINUTES WORKING: 2 HOURS EXAMINATION MATERIAL SUPPLIED BY THE UNIVERSITY: EXAMINATION BOOKLETS EXAMINATION MATERIAL SUPPLIED BY THE STUDENT: NIL, EXCEPT FOR WRITING IMPLEMENTS INSTRUCTIONS TO STUDENTS: Students are prohibited from having mobile phones or any other device capable of communicating information (either verbal or written) in their possessions during the examination NOTES MAY BE MADE QNLX ON THE EXAMINATION PAPER DURING PERUSAL TIME SEQTIQN A - TWO (2) QUESTIONS ONLY ARE TO BE ATTEMPTED SECTIQN B — TWO (2) QUESTIONS ONLY ARE TO BE ATTEMPTED ALL QUESTIONS ARE OF EQUAL VALUE Queensland University of Technology GUT GUT Gardens Point Kelvin Grove 1 SECTION A — Programmable Logic (Answer only 2 questions from this section) QUESTION 1 (a) Briefly describe the internal structure of programmable logic devices such as a GAL20V8, paying particular attention to the macrocell. ......... .. (5 marks) (b) A modulo-4 counter is required to count and display the numbers ‘—’ ‘3’ ‘6’ ‘9’ on a common cathode, 7-segment LED display. Three clock pulses after being a ‘-’(ie. the g segment) the counter reaches ‘9’. Once the counter reaches ‘9’ it is to stop counting, and remain displaying the ‘9’. M0dulo-4 COUNTER (GAL20V8) R Clock Pulse (a,b,c,d,e,f,g) (i) Draw a Transition Table, and hence produce equations for the segment outputs a,d and g. (assume that D-type flips are available). (ii) Show how you would incorporate the reset input (R) into the system, as indicated in the G 7 diagram above, so that the counter will be cleared to - on the next input clock pulse following a reset (R). (iii) Show how you would program the GAL20V8 system in WinCUPL, only writing the equations for segments a, d, and g . ....... .. (15 marks) QUESTIONZ (a) Simple PLD devices like GAL’s, have a single block of n macrocells (a block of 8 in the case of a GAL20V8), with dedicated output pins. Explain why devices such as the Altera Max7128 are called Complex PLD’s, and describe their main features. ........ .. (6 marks) (b) (i) Draw the truth table and hence obtain output equations for the segments a,b and c, in the 3-bit Gray to 7-Segment decoder shown below. GRAY P to Gray Q 7-Segment R DECODER bfijdae’f, (Max7128) (a’ g) Question 2 continued overleaf... ENBZ44T1.102 cont/ . . .. Question 2 continued (ii) Complete the following AHDL implementation of the Gray to 7-Segment Decoder, only writing equations for the segments a,b and c. SUBDESIGN DisplayGray3 ( p, q, r : INPUT; % Gray Code Input Seg7[a,b,c,d,e,f,g] : OUTPUT; % 7—seg display ) BEGIN Write this code, but only for the outputs a, b and c, in exam booklet. (Include the Begin and End) END; ....... .. (8 marks) (c) Complete the following code for implementing a 2-bit Binary Ripple Counter with asynchronous clear, using AHDL. (Note: Counter will require the flip flops to be individually connected as divide by 2 circuits) SUBDESIGN Bin2Counter ( Clk :INPUT; aClear :INPUT; % asynchronous Clear (Active Hi) A,B :OUTPUT; % A = Most Sig Bit ) VARIABLE A,B :DFF; % 2 D flipflops BEGIN Write this code (including Begin & End) in exam booklet END; ....... .. (6 marks) ENB244T1.102 cont/. . .. QUESTION 3 (a) Briefly describe the main differences between the CPLDs such as a Max7128 and FPGAs such as a CYCLONE II (2C3 5). ...... .. (6 marks) (b) (i) Produce the output equation Z for a 4 to 1 Data Selector (i.e. Mux) shown below. 81 SO A 4t01 3 DATA c SELECTOR D H—/ Selectlnputs (ii) Complete the following VHDL implementation of the Data Selector. ENTITY DataSeIector4 IS PORT (a, b, c, d :IN BIT; Z :OUT BIT); END DataSelector4; ARCHITECTURE circuit OF DataSelector4 IS BEGIN Write this code (include Begin & End) in exam book END circuit; ......... .. (4 marks) (c) (i) Produce the equations to implement a 3-bit counter that counts in the sequence: ABC = 000, 100, 110, 111, 000, using D-type flip Flops. Transition Table A Present State Next State Clock A B C A’ B’ C’ COUNTER B m C l aClear Empty (ii) Complete the following implementation of the counter in VHDL, including an asynchronous clear input (aClear), and an Empty output (ABC=000), as indicated above. ENTITY Counter IS PORT (Clock, aClear :IN BIT; a, b, c :OUT BIT; —— Counter Output Empty :OUT BIT); —— Empty = 000 END Counter; ARCHITECTURE circuit OF Counter IS BEGIN Write this code (including Begin & End) in your exam book END circuit; ........ ..( 10 marks) ENB244T1.102 cont/ . . .. 4 SECTIONB Microprocessors Answer only 2 questions fiom this section QUESTION 4 (a) A microprocessor system (16-bit address bus, 8—bit data bus, R/~W, E) is to have: 0 4K RAM 0000h -> OFFFh 0 Input Device (8-bits— Tri—state Buffer) 4000b 0 Output Device (8-bits- D-Type Register) 8000b 0 8K ROM E000h -> FF FFh The devices do not need to be fully decoded (i.e. they can also exist at unused addresses). Note; 0 The E pulse has to be incorporated into the chip selects of the RAM and Output device. 0 The 8-bit Tri—State Buffer is enabled with a 0 on its Output Enable line. 0 Data is clocked into the 8-bit Output Register on the pos going edge of its Clock input. (i) Design and produce a circuit diagram for the address decoder. (ii) Explain how the output device operates, to send data fiom the microprocessor to the outside world. ......... ..( 8 marks) (b) (i) Describe, with the aid of a diagram, how shift registers and clocks are used in synchronous serial communications, to transmit data from device A to device B. (ii) Show the pulse train and associated clock output to transmit the 8-bit binary number 10110010 using synchronous communications. ......... ..( 4 marks) (c) (i) Describe, with the aid of a diagram, the essential features of asynchronous serial communications, explaining why it is necessary to incorporate Start and Stop bits into the data stream, and use a x16 clock in the receiving system. (ii) Show the pulse train to transmit the 8-bit binary number 10110010 asynchronously, with no parity, and calculate the time to transmit it at 4800 Baud. ....... ..( 8 marks) QUESTION 5 (a) Describe the main fiinction of the Program Counter (PC), the Stack Pointer (SP), and the Condition Code Register (STATUS) in microprocessor system. Hence describe and how they operate when an interrupt occurs. ........ ..( 6 marks) (b) Assuming that a macro div8 is available to perform an 8—bit division write a subroutine in AVR assembly language to take a number in Temp (r16), convert it to 3 BCD digits and insert them into a BCD Buffer. ; Macro: diva (Note: no need to write, just use it) ;************* ; Divides two 8—bit numbers registers. ;Pre : Parl= numerator, Par2= denominator ;Post : r1 = Parl/ParZ, r0 = remainder Example of use: div r3, r4 ;post: r1 = r3/r4, r0 = remainder Question 5 continued overleaf... ENB244T1.102 cont/m. Question 5 continued ; SUBROUTINE: Bin8toBCD ;********************** ; Converts the binary number in Temp (r16) to 3 BCD digits and stores them in BCD Buffer ;Pre : Temp = 8—bit binary number (0 to 255) ;Post: BCD Buffer contains 3 BCD digits (hundreds digit first) .dseg BCDBuffer3: .byte 3 ; hundreds digit first .cseg Bin8toBCD: Write this code (including Bin8toBCD: and ret) in your exam book ret ........ ..( 7 marks) (0) (i) Describe, with the aid of a diagram, how you would set up the hardware on an ATMega16 to implement a 3—digit multiplexed 7-Segment Display system. (ii) Explain, with the aid of a flow chart, and fiagments of software code, how a software system could operate, to suitably display the 3—digits from the BCDBuffer3 of (b). ........ ..( 7 marks) QUESTION 6 (a) Describe, with the aid of diagrams, the main features and operation principles of the Timer systems in microcontrollers such as the AMega16, paying particular regard to input capture and output compare. ......... ..( 6 marks) (b) Show, with the aid of flow charts and assembly language code, how you would use Output Compare feature of Timer], in the ATMega16 microcontroller, to generate a continuous stream of interrupts (clock tick period = 5msecs), so that a 16-bit SecondsCounter could be incremented every second and cleared every 12 hours. Also a NewClockTickF lag is to be set every 5msecs, a NewSecFlag is to be set every one second, and an output pulse produced on PBO at a frequency of 0.5Hz. Assume there are predefined declarations that give all the relevant register addresses and flags, meaningful names such as T imerl Counter, T imerFlagReg, T imerIntEnableReg, T 1 OutCompAF lag, T I OutCompADataReg , etc. (Assume the processor is running at 4 MHz). ....... ..( 9 marks ) (c) Explain the advantages of incorporating interrupt driven processes (ie. background processes) into microprocessor system sofiware, so that there are both foreground and background tasks. Show, with examples, how these foreground and background processes could communicate with each other. ....... ..( 5 marks ) END OF PAPER BNB244T1.102 ...
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