hw-04 - CSE 379 Spring 2010 Homework #4 1. Using the MRS...

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CSE 379 Spring 2010 Homework #4 1. Using the MRS and MSR instructions, set the CPSR to disable normal interrupts and enable fast interrupts. Refer to the ARM Architecture Reference Manual for descriptions of MRS and MSR. 2. Identify two reasons why FIQs are able to be handled faster than IRQs. 3. In CSE 380, the address of the interrupt handler for FIQs was placed in memory at address 0x3C. The FIQ interrupt vector address is 0x1C. What instruction should be placed in the vector? 4. When an FIQ interrupt is being serviced, should the mode be set in the CPSR by copying the fiq_SPSR to the CPSR, or should the lower 5 bits simply be set to 10000 to place the processor in user mode? Justify your answer. 5. While executing the following instructions, a data abort occurs. When the processor starts to service the exception, the LDRSH instruction had been fetched and was in the process of being executed. The values of registers r0, r1, r8, r13, r14, and the CPSR are 0x0000A0F4, 0x000000E9, 0x00000001, 0x00000800, 0x000081E4, and
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This document was uploaded on 11/03/2011 for the course CSE 379 at SUNY Buffalo.

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hw-04 - CSE 379 Spring 2010 Homework #4 1. Using the MRS...

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