EE311 - EE311:ELECTRONIC DEVS & CIRCS 2:200901032188...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
> TOOLS > MY GRADES > VIEW ATTEMPTS > REVIEW ASSESSMENT: EE 311 EXAM 3 SPRING 2009 Review Assessment: EE 311 Exam 3 Spring 2009 User Atul * Chittora Submitted 4/27/09 11:34 AM Name EE 311 Exam 3 Spring 2009 Status Completed Score 100 out of 100 points Time Elapsed 0 hours, 35 minutes, and 44 seconds out of 2 hours and 0 minutes allowed. Instructions Question 1 10 out of 10 points The CMOS Inverter shown below has the following values : μ n C ox = 20 μA/V 2 μ p C ox = 10 μA/V 2 (W/L) n = 20 (W/L) p = 40 V tn = |V tp | = + 1.6 V V DD = + 8 V Determine the maximum current the inverter can sink for v o ≤ 0.25 V. Choose the closest value in mA. Selected Answer: Correct Answer: Question 2 10 out of 10 points
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
The CMOS Inverter shown below has the following values : μ n C ox = 20 μA/V 2 μ p C ox = 10 μA/V 2 (W/L) n = 20 (W/L) p = 40 V tn = |V tp | = + 0.8 V V DD = + 4 V λ n = λ p = 1/30 V -1 The input voltage v I is slowly swept from 0 V to a value V DD . Determine the peak current drawn from the power supply V DD during the sweep. Choose the closest value in mA. Selected Answer: Correct Answer: Question 3 10 out of 10 points The CMOS Inverter shown below has the following values : μ n C ox = 20 μA/V 2 μ p C ox = 10 μA/V 2 (W/L) n = 20 (W/L) p = 40 V tn = |V tp | = + 0.4 V V DD = + 2 V
Background image of page 2
If the total effective load capacitance is 15 pF, and if the inverter is switched at a frequency of 2 MHz, determine the average current drawn from the power supply V DD . Choose the closest value in mA. Selected Answer: Correct Answer: Question 4 10 out of 10 points Shown below is the cascode of 2 CMOS Inverter from Section 13.13 of PSPICE SIMULATION EXAMPLE. Minimum size devices are used with the following values : μ n C ox = 40 μA/V 2 μ p C ox = 12 μA/V 2 (W/L) n = (W/L) p = 3μm/3μm V tn = +0.7 V V tp = - 0.8 V λ n = 0.01 V -1 λ p = 0.03 V -1 V DD = +5 V C L1 = C L2 = 0.15 pF Note that the NMOS and PMOS
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Note that also V tn / V DD ≠ 0.2. Thus many of the formulas in Sedra- Smith are not applicable. Use the SPICE waveforms shown below to answer the question. Note that also C L1 = C L2 = 0.15 pF in place of the 0.1 pF shown below. For Inverter M1M2 : Determine the high-to-low propagation delay time t PHL . Choose the closest value in ns. Selected Answer: Correct Answer: Question 5 10 out of 10 points Assume that the basic CMOS Inverter has n = (W/L) n = 3.0 μm/ 2.0 p = 5.0 μm/ 2.0 μm. A complex CMOS logic gate is shown below. The inputs are A, A', B, & B', where A' denotes the inverse of A, etc. The CMOS logic
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

This document was uploaded on 11/03/2011 for the course EE 311 at SUNY Buffalo.

Page1 / 33

EE311 - EE311:ELECTRONIC DEVS & CIRCS 2:200901032188...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online