Verilog - CSE 341 Verilog HDL An Introduction Hardware Specification Languages Verilog Similar syntax to C Commonly used in Industry(USA Japan VHDL

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CSE 341 Verilog HDL An Introduction Hardware Specification Languages c Verilog h Similar syntax to C h Commonly used in a c VHDL h Similar syntax to ADA h Commonly used in a Government Contract Work a Academia a Europe Structural vs. Behavioral c Structural h Shows primitive components and how they are connected h Modules are defined as a collection of interconnected gates and other previously defined modules a Modules are built up to make more complex modules h The design describes the structure of the circuit c Behavioral h Shows functional steps of how the outputs are computed h Abstract description of how the circuit works h Does not include any indication of structure (implementation) details h Useful early in design process a Allows designer to get a sense of circuit’s characteristics before embarking on design process a After functionality is well defined, structural design may follow h Synthesis Tools a Generate implementation based on the behavioral specification c We’ll be using structural Overview c System is described as a set of modules consisting of: h Interface a (2) fundamental data types in Verilog C Nets Used to connect structures (eg. - gates) Need to be driven module Interface Description endmodule name ;
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c Reg Data storage element Retain value until overwritten by another value Don’t need to be driven h Description a Defines structure Modules C Instantiating modules can help make code easier to write, modify, read, and debug C Examples h Carry Lookahead Adder a Partial Full Adder a Carry Lookahead Unit h Barrel Shifter h 7-Segment Display Decoder C Basic Module Format C Structure module modulename ( port list ); parameters port declarations ( input or output ) wire declarations reg declarations submodule instantiations … text body … endmodule C Instantiations h modulename instance_name ( port list ); Datatypes C Net h Wire C Register h Reg h Static Storage Element Parameters C Parameters h Used to define constants in modules a Examples parameter and_delay=2, or_delay=1; and #and_delay (f,a,b);
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Primitive Structural Modules c Define the structure of the module h Form the module’s body c Format h gate # n ( output, inputs ) h Note: The integral delay ( # n ) may be neglected a If omitted, delay = 0 c Gates h and h or h nand h not h xor Identifiers c Names given to hardware objects h Wires (busses) h Registers h Memories h Modules c Alphanumeric c May Include: h _ h $ c May NOT Start With: h Number h $ Numbers c Syntax h Sized a Size Format Number a Size C Number of digits a Format (Base) C h (Hexadecimal) C d (Decimal) Default C o (Octal) C b (Binary) a Number C Number specified h Unsized a Format Number
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c Examples h 4’b1011 h 8’hfe902a30 h 2’d37
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This document was uploaded on 11/03/2011 for the course CSE 341 at SUNY Buffalo.

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Verilog - CSE 341 Verilog HDL An Introduction Hardware Specification Languages Verilog Similar syntax to C Commonly used in Industry(USA Japan VHDL

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