mult-div - CSE 341 Timing, Multiplication, & Division...

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CSE 341 Critical Path Discussion c Delay h Dependent upon inputs c Critical Path h Worst case scenario c Temporal Dependence of Delay h Delays are also dependent upon the previous set of inputs a State of Circuit c The delay through the circuit is NOT always equal to the critical path delay h It might be less, but NEVER greater than the critical path delay! c Example #1 h Consider a unit gate delay through the following circuit h Critical Path a Notice how there are multiple critical paths C This is not always the case h Timing Diagram a Notice the glitch y z x w v F y z x w v F v w x y z F Time 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
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c Example #2 h 16-bit Carry Lookahead Adder a 2 Levels of Carry Lookahead
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h Timing c c c c c c c c c Carry Lookahead Adder vs. Ripple Carry Adder Comparison h 16-bit Ripple Carry Adder vs. 16-bit Carry Lookahead Adder (with 2-Level Carry Lookahead) a Assume Unit Delay a Ripple Carry Adder C 3 levels of logic per full adder C 16 full adders C Critical Path Delay = 3 x 16 = 48 a Carry Lookahead Adder C 2 levels of logic in partial full adder 1 to generate S, once C is available C 2 levels of logic in carry lookahead unit C Critical Path Delay = 1 + 2 + 2 + 2 + 1 = 8 # 15 # 11 # 7 # 4 # 12 # 8 # 3 # 0 A A A A A A A A A A A A A A A A 0 4 8 12 1 5 9 13 2 6 10 14 3 7 11 15 G G G G G G G G G G G G G G G G 0 4 4 4 1 5 5 5 2 6 6 6 3 7 7 7 B B B B S S S S B B B B S S S S B B B B S S S S B B B B S S S S 0 4 8 12 0 4 8 12 1 5 9 13 1 5 9 13 2 6 10 14 2 6 10 14 3 7 11 15 3 7 11 15 P P P P P P P P P P P P P P P P C C C C C C C C C C C C C C C C C C C C PFA PFA PFA PFA Carry Lookahead Carry Lookahead #2 Carry Lookahead Carry Lookahead Carry Lookahead PFA PFA PFA PFA PFA PFA PFA PFA PFA PFA PFA PFA 0 4 4 4 1 5 5 5 2 6 6 6 3 7 7 7 0 4 4 4 0 1 5 5 5 4 2 6 6 6 8 3 7 7 7 12 G G G G j,i+3 j,i+3 j,i+3 j,i+3 P P P P C C C C j,i+3 j,i+3 j,i+3 j,i+3 i i i i G j,i+3 P C j,i+3 i G G G G G G G G G G G G G G G G i i i i i+1 i+1 i+1 i+1 i+2 i+2 i+2 i+2 i+3 i+3 i+3 i+3 P P P P P P P P P P P P P P P P C C C C C C C C C C C C C C C C i i i i i+1 i+1 i+1 i+1 i+2 i+2 i+2 i+2 i+3 i+3 i+3 i+3 i i i i i+1 i+1 i+1 i+1 i+2 i+2 i+2 i+2 i+3 i+3 i+3 i+3 G G G G i i+1 i+2 i+3 P P P P C C C C i i+1 i+2 i+3 i i+1 i+2 i+3
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Implementation #1 c Flowchart c Circuit Multiplicand Multiplier Product x n m n m bits x bits = ( + ) bits Test Multiplier0 32nd Repetition ? Multipler0 = 0 No Yes Multipler0 = 1 Multipler0 refers to LSB in Multiplier Product := Multiplicand + Product Right Shift Multiplier 1 bit Left Shift Multiplicand 1 bit Start Done Multiplicand Multiplier Product Shift Left Shift Right 64 bits 32 bits 64 bits Write 64-bit ALU Control Test Derived from David A. Patterson and John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface , 4 th edition, Elsevier, 2009, Figure 3.5, page 232 David A. Patterson and John L. Hennessy, Computer Organization and Design:
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mult-div - CSE 341 Timing, Multiplication, & Division...

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