Cad - Intro to CAD Tools Design entry and synthesis...

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Jon Turner / David M. Zar Design entry and synthesis Functional simulation Implementing circuit on S3 board Converting button pushes to action signals Debouncing buttons Intro to CAD Tools
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2 Using CAD Tools to Design Circuits Computer-Aided Design (CAD) tools have become essential to the design of digital circuits Design entry » schematic capture – graphic entry of circuit elements » hardware description languages and circuit synthesis • two major languages – VHDL and Verilog Simulation » functional simulation – verify logical correctness » timing simulation – verify that performance goals are met Timing analysis » analysis of delays in circuit components and wiring to verify that timing constraints are satisfied
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3 Simplified CAD Tool Flow Device Configuration Timing Analysis Implementation FPGA bitfile Timing Simulation VHDL testbench Functional Simulation netlist Synthesis VHDL source syntax check
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4 Using/Installing CAD Tools CAD tools installed in CEC (start Engineering Xilinx) » can be accessed on mirage using Remote Desktop Register for Xilinx University program (XUP) » www.xilinx.com/univ/ To install tools on your own computer, download webpack ( version 13.2 ) from » www.xilinx.com/support/download/index.htm » Follow installation instructions » accept the defaults if you can do not install in “Program Files” or any other path with spaces » install all the selected tools (including the programming drivers)
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5 Starting New Project Start Project Navigator by selecting » Start Programs Xilinx ISE Project Navigator Specify name and location File New Project XST ISim VHDL Specify Spartan3E Starter Board
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6 Creating VHDL Source File enter name Select VHDL Module Project New Source
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7 Entering VHDL Source and Checking VHDL editor Syntax check Error Messages select Implementation in mode menu
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8 Preparing to Simulate Project New Source select VHDL testbench
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9 Testbench for Calculator entity testCalc is end testCalc; architecture a1 of testCalc is ... begin uut: calculator port map(clk, clear, load, add, dIn, result); process begin -- clock process clk <= '0'; wait for 10 ns; clk <= '1'; wait for 10 ns; end process; tb : process begin clear <= '1'; load <= '1'; add <= '1'; dIn <= x"ff"; wait for 20 ns; clear <= '0'; load <= '1'; add <= '0'; dIn <= x"55"; wait for 20 ns; clear <= '0'; load <= '1'; add <= '1'; dIn <= x"aa"; wait for 20 ns; clear <= '0'; load <= '0'; add <= '1'; dIn <= x"55"; wait for 20 ns; ... clear <= '0'; load <= '0'; add <= '1'; dIn <= x"56"; wait for 20 ns;
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This document was uploaded on 11/06/2011.

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Cad - Intro to CAD Tools Design entry and synthesis...

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