DesignStudies2 - Design Studies Part 2 Data Queue Packet...

Info iconThis preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
Jon Turner/David M. Zar Data Queue Packet queue Design Studies – Part 2
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 Data Queue A queue is a data structure that stores a set of values so they can be retrieved in the same order they were stored. » operations are enqueue and dequeue » separate dataIn , dataOut ports allow simultaneous enqueue & dequeue » status signals: empty and full » implement using an array of data registers, a pair of pointers and a counter readPntr=1 cnt=4 writePntr=5 0 1 2 3 4 5 6 7 occupied words array clk enq deq dIn dOut empty, full
Background image of page 2
3 VHDL Specification entity queue is port ( clk, reset: in std_logic; enq, deq : in std_logic; dataIn : in word; dataOut : out word; empty, full : out std_logic); end queue; architecture arch of queue is constant qSize: integer := 16; type qStoreTyp is array(0 to qSize-1) of word; signal qStore: qStoreTyp; subtype pointer is integer; subtype counter is integer; signal readPntr, writePntr: pointer; signal count: counter; begin process (clk) begin array type declaration for storing data pointers and count register interface signals
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 if rising_edge(clk) then if reset = '1' then readPntr <= 0; writePntr <= (0); count <= 0; else if enq = '1' and deq = '1' then if count = 0 then qStore(writePntr) <= dataIn; writePntr <= writePntr + 1; count <= count + 1; else qStore(writePntr) <= dataIn; readPntr <= readPntr + 1; writePntr <= writePntr + 1; end if; elsif enq = '1' and count /= qSize then qStore(writePntr) <= dataIn; writePntr <= writePntr + 1; count <= count + 1; elsif deq = '1' and count /= 0 then readPntr <= readPntr + 1; count <= count - 1; end if; end if; end if; end process; dataOut <= qStore(readPntr); empty <= '1' when count = 0 else '0'; full <= '1' when count = qSize else '0'; end arch; simultaneous enq, deq defining output signals enq, deq operations
Background image of page 4
5 Simulation Results incoming values stored values queue full condition and simultaneous enq and deq outgoing values
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
6 Packet FIFO Store variable length packets in FIFO order » packets received and sent word-by-word Left interface signals include » start-of-packet – high during first clock tick of packet » ack output high if enough room to store arriving packet » error output high if packet length out of range (dIn = [3, 6]) Right interface signals include » ok2send – when high, circuit sends packet if it has one
Background image of page 6
Image of page 7
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 19

DesignStudies2 - Design Studies Part 2 Data Queue Packet...

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online