Seq-1 - Sequential Circuits Part 1 Clocked sequential...

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Jon Turner/David M. Zar Clocked sequential circuits and state machines From circuit description to state diagram From state diagram to VHDL specification Verifying state machines Sequential Circuits – Part 1
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2 Clocked Sequential Circuits In sequential circuits, output values may depend on both current inputs and stored information » clocked sequential circuits store information in flip flops » stored information referred to as state of the circuit Next state logic determines new stored values Synchronous outputs depend only on stored values and change following clock edge Asynchronous outputs can change as inputs change next state logic Flip-flops inputs asynchronous outputs next state current state clock signal sync output logic async output logic synchronous outputs
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3 Fair Arbiter Controls access to a shared resource » inputs: request0, request1 » outputs: grant0, grant1 » grants asserted in response to inputs » if requests from both clients, favor least-recently-served CLK r0 r1 g0 g1 Can we do this with a combinational circuit? » What needs to be remembered? Incomplete Spec? » How long should the grant be asserted? » Can a new request come from the device with a pending grant?
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4 State Tables and State Diagrams The fair arbiter is example of a state machine The behavior of a state machine can be conveniently specified using a state diagram A state table is an equivalent representation idle0 busy0 idle1 busy1 Current State Input r0 r1 0 0 1 x 0 1 1 x 0 x 0 0 x 1 1 0 x 1 x 0 Next State Output g0 g1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 idle0 busy0 busy1 busy0 idle1 idle1 busy1 busy0 busy1 idle0 1x idle0/00 busy0/10 busy1/01 idle1/00 00 00 1x 0x x0 x1 10 01 x1 r0 r1 g0 g1
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5 VHDL for Fair Arbiter entity fairArbiter is port( clk, reset, request0, request1: in std_logic; grant0, grant1: out std_logic); end fairArbiter; architecture a1 of fairArbiter is type stateType is (idle0, idle1, busy0, busy1); signal state: stateType; begin process(clk) begin if rising_edge(clk) then if reset = '1' then state <= idle0; else case state is when idle0 => if request0 = '1' then state <= busy0; elsif request1 = '1' then state <= busy1; end if; when busy0 => if request0 = '0' then state <= idle1; end if; ... end case;
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This document was uploaded on 11/06/2011.

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Seq-1 - Sequential Circuits Part 1 Clocked sequential...

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