Verification

# Verification - Design Verification Use of assertions in...

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Jon Turner/David M. Zar Use of assertions in circuits and testbenches Testing small combinational circuits Testing state machines Techniques for making testing more automatic Strategies for larger circuits Design Verification

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2 Importance of Verification Bugs in digital circuits can be very costly » “re-spins” of custom circuits can cost several \$million » delays caused by re-spins can lower product sales » buggy products may have to be recalled and replaced » bugs in safety-critical products can lead to legal liabilities Companies invest lots of effort in circuit verification » projects often have more verification engineers than design engineers » verification engineers actively try to “break” circuits How are circuits checked for correctness? » simulation – both at system level and individual modules » formal verification – useful, but limited application
3 Assertions in Circuit Specifications Check consistency of procedure outputs procedure minMax( a, b: in SLV(7 downto 0); x, y: out SLV(7 downto 0)) is begin if a < b then x <= a; y <= b; else x <= b; y <= a; end if; assert(x <= y); end procedure minMax; Check range of input argument procedure update(i: in SLV(4 downto 0); v: in SLV(7 downto 0)) is begin assert(0 <= int(i) and int(i) <= 23); if tbl(int(i)).valid = ‘1’ then tbl(int(i)).value <= v; end if; end procedure update;

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4 Testing Combinational Circuits Small circuits can be tested exhaustively Example: 4 bit 2s complement circuit » complement data input when control input (c) is high, else output=input » note: 5 inputs, so 32 distinct input values entity negate is port ( c: in std_logic; -- negate when c = high, otherwise dout=din din : in std_logic_vector(3 downto 0); dout : out std_logic_vector(3 downto 0)); end negate; architecture a1 of negate is begin dout <= (not din) + 1 when c = '0' else din; end a1; note: logic reversed
5 Testbench for Negate library ieee; ... use work.txt_util.all; ... entity testNegate is end testNegate; architecture a1 of testNegate is ... begin uut: negate port map(c, din, dout); tb : process begin c <= '0'; for i in 0 to 15 loop din <= conv_std_logic_vector(i,4); wait for pause; assert (dout = din) report "error when c=0 i=" & str(i); end loop; c <= '1'; for i in 0 to 15 loop . . end loop; assert (false) report "Simulation ended normally." severity failure; end process; end a1; include txt_util.vhd as a project source iterate through all dIn values assertion used to verify correctness str() converts integer to string convert integer to 4 bit logic vector

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6 Simulation Results bug apparent in waveform window also reported on simulation “console” due to assertion violations
7 A Bigger Example Some circuits are too big to check manually, but

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## This document was uploaded on 11/06/2011.

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Verification - Design Verification Use of assertions in...

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