Vhdl2 - Designing with VHDL part 3 signal attributes arrays...

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Jon Turner / David M. Zar signal attributes arrays and records variables functions and procedures assertions packages Designing with VHDL – part 3
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2 Signal Attributes For signal x: std_logic_vector(15 downto 0) , » x’left =15, x’right =0 » these are referred to as attributes of x » other attributes include x’high (=15), x’low (=0), x’range (=15 downto 0) and x’length (=16) Signal attributes can be used to write code that is less dependent on specific signal lengths » for example x(x’high) <= ‘1’; x(x’low+3 downto x’low) <= x”c”; x <= (x’high => ‘1’, x’low => ‘1’, others => ‘0’); This can make code easier to change and is useful when writing modules with generic signal lengths
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3 Arrays of std_logic_vectors -- using these constants subtype word is std_logic_vector(wordSize-1 downto 0); type regFileTyp is array(0 to regFileSize-1) of word; signal reg: regFileType; -- we can write things like reg(2) <= reg(1) + reg(4); reg(3 downto 0) <= reg(7 downto 4); reg(3)(5) <= 1 ; Synthesizer can implement such arrays using registers constructed from flip flops Sometimes can be implemented using memory blocks » depends on how the circuit is used » for large arrays of words that are accessed one at a time, synthesizer will typically use a memory block
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4 Defining 2d Constant Arrays Constant arrays can be used to define tables of values subtype asciiChar is std_logic_vector(7 downto 0) type hex2AsciiMap is array(0 to 15) of asciiChar; constant hex2Ascii: hex2AsciiMap := ( x"30", x"31", x"32", x"33",x"34", -- 0-4 x"35", x"36", x"37",x"38", x"39", -- 5-9 x"61", x"62",x"63", x"64", x"65", x"66" -- a-f ); ... ascii3 <= hex2Ascii(int(x”3”));
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Vhdl2 - Designing with VHDL part 3 signal attributes arrays...

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