VHDLp1 - Using VHDL to Design Digital Circuits Part 1 assignments processes and if-then-else avoiding unintended storage separation principle Jon

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Jon Turner/David M. Zar assignments processes and if-then-else avoiding unintended storage separation principle Using VHDL to Design Digital Circuits – Part 1
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‹#› Hardware Description Languages HDL s allow designers to work at a higher level of abstraction than logic gates HDL descriptions can be » compiled to a low level form that can be simulated for logical correctness, timing analysis, etc. » converted to a circuit specification using a library of primitive components and timing/area constraints But don’t confuse hardware design with software » HDL descriptions for circuits must translate to physical components that can fit in space available and meet timing specs » circuits are inherently parallel with many things going on at once
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‹#› Binary Coded Decimal to Excess-3 Code W=A+BC + BD X=B C+B D+BC D Y=CD+C D Z=D -- Binary Coded Decimal to Excess 3 converter -- ABCD is 4 bit input value -- WXYZ is 4 bit output value -- WXYZ = ABCD + 3 entity bcd2xs3 is port ( A,B,C,D : in std_logic; W,X,Y,Z : out std_logic ); end bcd2xs3; architecture a1 of bcd2xs3 is begin W <= A or (B and (C or D)); X <= ((not B) and (C or D)) or (B and (not C) and (not D)); Y <= C xnor D; Z <= not D; end a1 start comment with “ -- entity declaration defines module interface signal assignments equivalent to logic equations ABCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 WXYZ 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 BCD xs3 decimal 0 1 2 3 4 5 6 7 8 9 meaning of VHDL is specified circuit not sequential execution!
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‹#› bcd2xs: Using Vector Assignments -- Binary Coded Decimal to Excess 3 converter -- xs3 <= bcd + 3 entity bcd2xs3 is port ( bcd:in unsigned(3 downto 0); xs3:out unsigned (3 downto 0) ); end bcd2xs3; architecture a1 of bcd2xs3 is begin xs3(3) <= bcd(3) or (bcd(2) and (bcd(1) or bcd(0))); xs3(2) <= ((not bcd(2)) and (bcd(1) or bcd(0))) or (bcd(2) and (not bcd(1)) and (not bcd(0))); xs3(1 downto 0) <= (bcd(1) xnor bcd(0)) & not bcd(0); end a1; logic vector declarations & concatenates signals
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bcd2xs: Using “excess-3” -- Binary Coded Decimal to Excess 3 converter -- xs3 <= bcd + 3 entity bcd2xs3 is port ( bcd:in unsigned(3 downto 0); xs3:out unsigned(3 downto 0) ); end bcd2xs3; architecture a2 of bcd2xs3 is begin xs3 <= bcd + b"0011"; -- or -- xs3 <= bcd + 3; -- or -- xs3 <= bcd + x”3”; end a2; using binary addition operator, add three
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VHDLp1 - Using VHDL to Design Digital Circuits Part 1 assignments processes and if-then-else avoiding unintended storage separation principle Jon

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