WashU2-2 - Design of the WashU-2 Processor Part 2 Processor execution cycle Instruction timing VHDL specification of processor Jon Turner/David M

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Jon Turner/David M. Zar Processor execution cycle Instruction timing VHDL specification of processor Design of the WashU-2 Processor – Part 2
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2 Processing Cycle Instruction fetch » PC used to load IREG from memory » PC is incremented Instruction decode » first 4 bits of retrieved instruction are decoded to determine what to do • in some cases additional bits » appropriate circuitry activated Instruction execution » retrieve additional memory words » write to memory » modify PC or ACC contents » may take different amounts of time to complete Fetch/decode halt negate branch brZero. .. dStore mLoad dLoad iLoad dStore iStore Add,And iBranch
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3 IREG decode LD Addr Bus Data Bus state tick Control Logic ( combinational circuit ) mem_en mem_rw ACC ALU compare OP IAR PC + Instruction Fetch 1. PC value on Abus 3. Load IREG 4. Increment PC 2. Memory contents on Dbus 1. mem_en <= 1 3. mem_en <= 0
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4 Instruction Execution Direct Load » transfer data from memory to ACC , using high 4 bits of PC and low 12 bits of instruction word as memory address » requires asserting of memory signals and loading ACC Conditional branch » determine if ACC =0 (or >0 or <0) » if so, add sign-extended low 8 bits of instruction to PC Indirect store » transfer data from memory to Indirect Address Register ( IAR ) using high 4 bits of PC and low 12 bits of instruction word as memory address » transfer data from ACC to memory, using IAR for address » requires placing IAR value on address bus and asserting signals to perform memory write
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5 IREG decode LD Addr Bus Data Bus state tick Control Logic (combinational circuit) mem_en mem_rw ACC ALU compare OP IAR PC + Add Instruction Execution 1. mem_en <= 1 2. Memory contents on Dbus 1. IREG value on Abus 4. Load sum into ACC 3. ALU adds values 3. mem_en <= 0
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6 mem_en mem_rw Signal Timing for Processor Negate mLoad Branch value returned on next tick IREG loaded PC incremented ACC loaded PC loaded ACC loaded PC value on Abus clk pc ireg acc Fetch abus dbus pc ram dbus clk mem_en mem_rw ireg acc abus dbus pc ireg ram dload, add, and
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7 Signal Timing for Processor dStore ireg acc clk mem_en mem_rw abus dbus iar acc iLoad ireg iar ram ram clk mem_en mem_rw iar abus dbus iStore ireg iar ram acc
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This document was uploaded on 11/06/2011.

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WashU2-2 - Design of the WashU-2 Processor Part 2 Processor execution cycle Instruction timing VHDL specification of processor Jon Turner/David M

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