WashU2-3 - Design of the Washu-2 Processor Part 3...

Info iconThis preview shows pages 1–9. Sign up to view the full content.

View Full Document Right Arrow Icon
Jon Turner/David M. Zar Supporting Components Design of the Washu-2 Processor – Part 3
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 The WashU-2 on the S3 board Display showing •internal registers •memory locations Field Programmable Gate Array (FPGA) implements processor Push buttons •reset •single step •load data into memory Slide switches VGA display connector Program button configures FPGA Knob for entering data
Background image of page 2
3 Using the WashU-2 Processor Reset by setting pressing “north” button » restarts processor, but does not re-initialize memory » re-program device to re-initialize memory Using single step mode » press west button to enter single-step mode, press again to execute one instruction » press south button to exit single step mode Using display » display shows IREG ACC SnoopAdr PC IAR SnoopData » when switch(3)=0, knob controls Snoop Address register » when switch(3)=1, knob controls Snoop Data register » press down on knob to change higher-order digits
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 Support Components in S3 Version display buffer drives VGA display interface Console includes several internal processes displays CPU registers and snoop registers implements single-step operation by pausing processor implements snooping and memory update by accessing memory (pausing processor as it does so) Data Bus Address Bus Memory 0000 0001 0002 0003 0004 0005 0006 0007 FFFF . . . EN Processor IREG PC ACC IAR reset buttons { hv } Sync dispVal Console snoopAddr snoopData knobIntf dispBuf . . . deBouncer lcdDisplay knob RW EN RW pause regSel cpuReg switches lcd Signals
Background image of page 4
5 Simulation – Single Step Operation instructions execute then pause pause drops for each subsequent button press button press to enter SS mode button press to do one instruction button press to resume normal operation back to normal processor pauses after finishing instruction
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
6 Knobs and Snooping button press updates M[10], program then updates sum input word and sum knob changes increment snoopAdr then snoopData
Background image of page 6
7 button press Detailed View processor paused for memory write input value from snoopData knob rotation increments snoopData
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
8 entity console is port( clk: in std_logic; btn: in buttons; knob: in knobSigs; swt: in switches; led: out LEDs; resetOut: out std_logic; pause: out std_logic; -- pause CPU -- memory signals memEnIn, memRwIn: in std_logic; memEnOut, memRwOut: out std_logic;
Background image of page 8
Image of page 9
This is the end of the preview. Sign up to access the rest of the document.

This document was uploaded on 11/06/2011.

Page1 / 16

WashU2-3 - Design of the Washu-2 Processor Part 3...

This preview shows document pages 1 - 9. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online