Unformatted text preview: ECE 342: Electronic Circuits (Fall 2011) Instructor: Professor N. R. Shanbhag Homework 3 (Due: Sep. 12, 5pm)
1. Problem 13.26, only do part (b). 2. Consider a matched CMOS inverter circuit as shown in Fig. 1, with Vtn0 = -Vtp0 = 0.3V, VDD = 1.2V,
2φFn = -2φFp =0.65V, γn = -γp = 0.5V1/2. Figure 1.
If the maximum expected noise amplitude at the inverter input is Vnoise,max = 0.55V, find the values
of body bias voltages VBn, VBp that will result in both noise margins being greater than Vnoise,max.
|2 | .
Hint: For both NMOS and PMOS, 3. Problem 13.42. 4. Consider the logic circuit as shown in Fig. 2.
a. Write down the Boolean expression realized by the logic circuit.
b. Compute VOL and VOH.
The circuit parameters are Vtn0 = -Vtp0 = 0.4V, VDD = 2.5V, 2φFn = -2φFp = 0.65V, γn = -γp = 0.5V1/2.
c. Discuss the issues that are preventing the design from qualifying as a good logic circuit, in terms of
noise immunity and speed. Department of Electrical and Computer Engineering, University of Illinois at Urbana‐Champaign Page 1 ECE 342: Electronic Circuits (Fall 2011) Instructor: Professor N. R. Shanbhag VDD A Y Figure 2. 5. Implement the logic function Y = AB + C in CMOS logic, using no more than 8 transistors. Assume that
only the uncomplemented variables ( A, B, C ) are available. 6. Problem 13.55. Department of Electrical and Computer Engineering, University of Illinois at Urbana‐Champaign Page 2 ...
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- Spring '11
- logic circuit, CMOS inverter circuit, Professor N. R., N. R. Shanbhag