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Brown & Vranesic - Fundamentals of Digital Logic with VHDL (2nd) --solution chap2

# Brown & Vranesic - Fundamentals of Digital Logic with VHDL (2nd) --solution chap2

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Unformatted text preview: Chapter 2 2.1. The proof is as follows: (m + y) - (m + z) : mm + m2 + my + yz : m + m2 + my + yz : m(1+z+y)+yz : m - 1 + yz : m + yz 2.2. The proof is as follows: (m + y) - (m + y) : mm + my + my + yy : m + my + my + 0 : 5150 + 3/ + g) : m : II} 2.3. Proof using Venn diagrams: I H X+_y X+Z N X+y-z (X+y)(X+z) 2—1 2.4. Proof of 150, using Venn diagrams: >< “<1 A similar proof is constructed for 15b. 2.5. Proof using Venn diagrams: 4% X1+X2+X3 «>3 X1+X2+X3 a “a V (X1+X2 +X3)-(X1+X2+3(3) 2—2 2.6. A possible approach for determining whether or not the expressions are valid is to try to manipulate the left and right sides of an expression into the same form, using the theorems and properties presented in section 2.5. While this may seem simple, it is an awkward approach, because it is not obvious what target form one should try to reach. A much simpler approach is to construct a truth table for each side of an expression. If the truth tables are identical, then the expression is valid. Using this approach, we can show that the answers are: (a) Yes (b) Yes (c) No 2.7. Timing diagram of the waveforms that can be observed on all wires of the circuit: 2—3 2.8. Timing diagram of the waveforms that can be observed on all Wires of the circuit: 2.9. Starting with the canonical sum—of—products for f get f : T1T2113+111213+111213+111213+111213+111213+111213 T2T3+1213+1213+1213)+12(1113W1113+1113+1113) 3QI112+I112+I112+I112) T2 (T3 +11:3) +11:2(T3 +11:3)) +11:2(T1(T3 W11:3) +11:1(T3 +11:3)) 3QI1Q12+12)+I1Q12+12)) T2- 1+ 12 l)+.1:.2(T1-1+1L'1-l)+11:3(T1-l+11:1-l) 12+12)+12(11+11)+13(11+11) : 11:1-l+11:2-l+11:3-l : 11:1+1L'2+1L'3 : III1 M Q M M 2.10. Starting with the canonical product—of—sums for f can derive: f : ’I}1 W.’I}2WWE3 I1WWEZWWIII3)(II}1+E2+E3)- Q ) Q 1 W112WT3) 1:1:) 1:3 ) ’I}1 WWII52W1I53 ZNI ,_t l N w l N w wvv 11:1 W11:2 W 11:3)(11:1 W T2 W T3)) - ;;1 W11:2 W11:3)(T1 W 11:2 W 113)) AA :~ H l c N) l l Dix. ~~‘I 03 V NI ,_t l N w l l N o: N w v Q Q Q Q Q Q Q 1 L1 W11:2)(1L'1 +T2)1: : (11:1 + E2E2)(E1 + (1)2(1)3) : 11:1(E1 + (1)2(1)3) : 11:1E1 + (1)1(1)2(1)3 W (1) 1 (1) 2 (1) 3 2.11. Derivation of the minimum sum—of—products expression: f : (1)1(1)3 + (1)152 + E1(1)2(1)3 + E1E2E3 : (1)1(E2 + (1)2)(1)3 + (1)1?2 (13 + (1)3) + E1(1)2(1)3 + E1E2E3 : 11:1E2E3 + (1)1(1)2(1)3 + E1E2E3 + E1:I:2:I:3 + E1E2E3 : (1)1(1)3 W (11:1 + E1):I:2:I:3 + (11:1 + E1)E2E3 : (1)1(1)3 W (1)2(1)3 + E2E3 2.12. Derivation of the minimum sum—of—products expression: f : E1E2E3 + 11:11:21)); + 11:1E2E3E4 : 11:1E2E3(E4 + 11:4) + (1)1(1)2(1)4 + 11:1E2E3E4 : (1)1(1)2(1)3(1)4 + 11:1E2E3E4 + (1)1(1)2(1)4 + 11:1E2E3E4 : (1)1(1)2(1)3 W 11:1E2 (E3 + 11:3)E4 +(1)1(1)2(1)4 : (1)1(1)2(1)3 W E1E2E4 + 11:11:21)); f W 11:4) E z: W (1)4)((1)1 + E2 + E3 + 11:4) I 2 (11:1 + E2 + 11:4 (11:3 + E3)) 1 N H 1 1 HI N) 1 1 N OJ 1 (11:1 W 11:3 W :: (1)1 WW (1)3 W () N g; N ,_t 1 1 N N) 1 1 N w 1 N g; N ,_t 1 1 N N) 1 1 N w ,_t 1 1 1 1 N w \ (1)1 WW (1)3 W () é§ ,_t 1 N g; N ,_t 1 1 N N) 1 1 N w 1 N g; vvvvv WW (1)3 W () ,_t 1 \ ~| N) 1 1 ~ g; v H bhﬂbb AAAAA N ,_t 1 1 w 1 1 N w vvvvv N 1—1 1 1 N N) 1 1 N 03 Ahrxx-x N ,_t 1 \ é%| \. N) 1 1 N g; v (1)1 WW (1)3 WW () N g; 2.14. Derivation of the minimum product—of—sums expression: f : (11:1 W 11:2 + (1)3)((1)1 + E2 + 11:3)(E1 + E2 + (1)3)((1)1 + 11:2 W E3) : ((1)61 + 11:2) + (1)3)(((1)1 + 11:2) + E3)(:I:1 + (E2 + 11:3))(E1 W (E2 + 11:3» : ((1)1 WW (1)2)(52 ‘1’ 51/3) 2.15. ((1,) Location of a11minterms in a 3—variab1e Venn diagram: A AVA v 2—5 ”10 (b) For f : 11:1T2:I:3 + 11:1:I:2 + T1903 have: Xl'XZ'X3 Xl'XZ Xl'X3 Therefore, f is represented as: f : 11:3 + 11:1:I:2 2.16. The function in Figure 2.18 in Venn diagram form is: «33 V 2.17. In Figure P210, it is possible to represent only 14 minterms. It is impossible to represent the minterms T1T2:I:3:I:4 and 11:13:2E3T4. In Figure P2.1b, it is impossible to represent the minterms 11:13:2T3E4 and 11:1:I:2:I:3T4. 2.18. Venn diagram for f : Eliza/3%; + 11:1:I:2:I:3:I:4 + \$111.? is 5" 4" 2—6 2.19. The simplest SOP implementation of the function is f : E1:I:2:I:3 + 11:1E2E3 + 11:1:I:2E3 + 11:1:I:2:I:3 : (E1 + 11:1):I:2:I:3 + 11:1(E2 + 11:2)E3 : 11521153 + 11:1E3 2.20. The simplest SOP implementation of the function is f : E1E2:I:3 + E1:I:2:I:3 + 11:1E2E3 + 11:1:I:2E3 + 11:1:I:2:I:3 ( i E1 E2 + 11:2):I:3 + 11:1(E2 + 11:2)E3 + (E1 + 11:1):1:2:I:3 I 1 13 + 11:1E3 + 11521153 Another possibility is f : E1:I:3+:I:1E3+:I:1:I:2 2.21. The simplest POS implementation of the function is f : (11:1 W 11:2 + 11:3)(:I:1 W E2 + 11:3)(E1 + 11:2 + E3) : ((1)61 + 11:3) + 11:2)((:1:1 + 11:3) + E2)(E1 + 11:2 + E3) : (11:1 W 11:3)(E1 +1162 " 11:3) 2.22. The simplest POS implementation of the function is f : (:51 W .752 + :1:3)(:1:1 +:1:2 + E3)(E1 + 11:2 + E3)(E1 + E2 + E3) : ((1)61 + 11:2) + 11:3)((:I:1 + 11:2) + E3)((E1 + 11:3) + 11:2)((E1 + 11:3) + E2) : ((1)1 ,, 1152)(E1 + 73) 2.23. The lowest cost circuit is deﬁned by f(:1:1,11:2,11:3) : 11:1:I:2+:I:1:I:3+:I:2:I:3 2—7 2.24. The truth table that corresponds to the timing diagram in Figure P23 is ~ ,_t ~ N) 03 “a HHHHOOOO HHOOHHOO ﬁ—‘Oﬁ—‘Oﬁ—‘Oﬁ—‘O OHHOHOOH The simplest SOP expression is f : \$15253 + 5111:2113 + 11452113 + 11:13:2E3. 2.25. The truth table that corresponds to the timing diagram in Figure P24 is I 1 :1:2 I 3 f 0 0 0 0 0 0 l l 0 l 0 l 0 l l l l 0 0 l l 0 l 0 l l 0 0 l l l l The simplest SOP expression is derived as follows: f : \$152.13 + \$111353 + 5111:2113 + 11.15253 + 11:1:I:2:I:3 : E1 \$2 + (152)1153 + 7172(73 +1153) + (71 + (1)1)11521153 +1151E2E3 : T1 - l - 11:3 + T1902 - l + l - 11:2:I:3 + 11:1E2E3 : \$1113 + \$111.? + 11:2:I:3 + 11.15253 2—8 2.26. ((1,) f 1000010000100001 HOV 0101010101010101 71\$ 0011001100110011 0000111100001111 0000000011111111 (b) The simplest POS expression is f :(1151 +g1)(51 + 7J1)(fI/'0 +?0)(50 + 3/0) 1000110011 2.27. ((1,) 0101010101 0011001100 0000111100 0000000011 2—9 (b) The canonical SOP expression is f : 11:1:I:0y1y0 + 11:1:I:0y1y0 + 11:1:I:0y1y0 +1101igy1§0 + 11:1igylyo +1201igy1y0 +:I:1:1:0y1y0 + 11:11:0y1y0 + 11:1:I:0y1y0 + 11:1:I:0y1y0 (C) The simplest SOP expression is f : 11:1:I:0 + glyo + 114% +z1:0y1 2.28. Using the Ciruit in Figure 2250, as a starting point, the function in Figure 2.24 can be implemented using NAND gates as follows: 2.29. Using the Ciruit in Figure 2.25!) as a starting point, the function in Figure 2.24 can be implemented using NOR gates as follows: 2—10 2.30. The circuit in Figure 2.33 can be implemented using NAND and NOR gates as follows: 2.31. The minimum—cost SOP expression for the function f (11:1, 11:2, 11:3) : Z m(3, 4, 6, 7) is f : 11:13; + 11:2:I:3 The corresponding circuit implemented using NAND gates is 13H 2.32. A minimum—cost SOP expression for the function f (11:1, 11:2, 11:3) : Z m(l7 3, 4, 6, 7) is f : 11:1:I:2 + 11:13; + T1903 The corresponding circuit implemented using NAND gates is 2—11 2.33. The minimum—cost POS expression for the function f (11:1, 11:2, 11:3) : Z m(3, 47 6, 7) is f : (11:1 + 11:3)(:I:2 + 73) The corresponding circuit implemented using NOR gates is 2.34. The minimum—cost POS expression for the function f (11:1, 11:2, 11:3) : Z m(l7 3, 47 6, 7) is f : (11:1 + 11:3)(E1 + 11:2 + 73) The corresponding circuit implemented using NOR gates is X1 iDo—f 2.37. The circuit in Figure 2250, can be implemented using; module prob2_37 (X1, X2, X3, f); input X1,X2,X3; output f; not (notX1, X1); not (notX2, X2); not (notX3, X3); and (a, notXl, notX2, X3); and (b, notX1, X2, notX3); and (c, Xl, notX2, notX3); and (d, X1, X2, X3); or (f, a, b, c, d); endmodule 2—12 2.38. The Circuit in Figure 2.25!) can be implemented using; module pr0b2_38 (X1, X2, X3, f); input X1,X2,X3; output f; not (n0tX1, X1); not (n0tX2, X2); not (n0tX3, X3); or (a, X1, X2, X3); or (b, n0tX1, n0tX2, X3); or (C, n0tX1, X2, n0tX3); or (d, X1, n0tX2, n0tX3); and (f, a, b, c, d); endmodule 2.39. The simplest Circuit is Obtained in the POS form as f : (:51 + 11:2 + 11:3)(E1 + \$2 + \$3) Verilog code that implements the Circuit is module pr0b2_39 (X1, X2, X3, f); input X1,X2,X3; output f; r( ,X1,X2,X3); r (h, ~X1, ~X2, ~X3); and (f, g, h); 0 0 endmodule 2.40. The simplest Circuit is Obtained in the SOP form as f : \$2 + E11153 +1151E3 Verilog code that implements the Circuit is module pr0b2_40 (X1, X2, X3, f); input X1,X2,X3; output f; assign f = ~X2 | (~X1 & X3) | (X1 & ~X3); endmodule 2—13 2.41. The Verilog code is module pr0b2_41 (x1, x2, x3, x4, f1, f2); input x1,x2,x3,x4; output f1, f2; assign f1 = (x1 & ~x3) | (x2 & ~x3) | (~x3 & ~x4) | (x1 & x2) | (x1 & ~x4); assign f2 = (x1 | ~x3) & (x1 | x2 | ~x4) & (x2 | ~x3 | ~x4); endmodule 2.42. The Verilog code is module pr0b2_42 (x1, x2, x3, x4, f1, f2); input x1,x2,x3,x4; output f1,f2; assign f1 = (x1 & x3) | (~X1 & ~x3) | (x2 & x4) | (~x2 & ~x4); assign f2 = (x1 & x2 & ~x3 & ~x4) | (~X1 & ~x2 & x3 & x4) | (X1& ~X2 & ~X3 & X4) | (~X1& X2 & X3 & ~X4); endmodule 2—14 Chapter 3 3.1. ((1,) X1 X2 X3 f 0 0 0 0 0 0 l l 0 l 0 l 0 l l 0 l 0 0 l l 0 l 0 l l 0 0 l l l l (b) #transistors : NOT_gates X 2 + AND_gates X 8 + OR_gates : 3x2+4><8+l><10:48 3.2. ((1,) In problem 3.1 the canonical SOP for f is f : Eliza/'3 + Elilﬁgig + (liligig + (1511131153 This expression is equivalent to f in Figure P32, as derived below. XII—(2X3 + XIX 2273 + X1 272273 + X1X2X3 (b) Assuming the multiplexers are implemented using transmission gates #transistors : NOT_gates X 2 + MUXes X 6 : 1 X 2 + 3 X 6 : 20 3—1 ...
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Brown & Vranesic - Fundamentals of Digital Logic with VHDL (2nd) --solution chap2

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