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Brown & Vranesic - Fundamentals of Digital Logic with VHDL (2nd) --solution chap3

# Brown & Vranesic - Fundamentals of Digital Logic with VHDL (2nd) --solution chap3

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Unformatted text preview: Chapter 3 3.1. ((1,) X1 X2 X3 f 0 0 0 0 0 0 l l 0 l 0 l 0 l l 0 l 0 0 l l 0 l 0 l l 0 0 l l l l (b) #transistors : NOT_gates X 2 + AND_gates X 8 + OR_gates : 3x2+4><8+l><10:48 3.2. ((1,) In problem 3.1 the canonical SOP for f is f : Eliza/'3 + Elilﬁgig + (Eligig + (1511131153 This expression is equivalent to f in Figure P32, as derived below. XII—(2X3 + XIX 2273 + X1 272273 + X1X2X3 (b) Assuming the multiplexers are implemented using transmission gates #transistors : NOT_gates X 2 + MUXes X 6 : 1 X 2 + 3 X 6 : 20 3—1 3.3. ((1,) A SOP expression for f in Figure P33 is: f : (11:1 W 11:2) EB 11:3 : (11:1 W 11:2)E3 + (11:1 EB 11:2):I:3 : (Eligig + Elilﬁgig + Eliza/'3 + 11511131153 which is equivalent to the expression derived in problem 3.2. (b) Assuming the XOR gates are implemented as shown in Figure 3.61!) #transistors : XOR_gates X 8 : 2 x 8 : 16 3.4. Using the Circuit The number of transistors needed is 16. 3.5. Using the Circuit The number of transistors needed is 20. 3.6. ((1,) 0 0 0 1 0 0 1 1 0 l 0 l 0 l l l l 0 0 l l 0 l 0 1 1 0 0 l l l 0 3—2 (b) The canonical SOP expression is f : 11:1:I:2:I:3 + 11:1:I:2:I:3 + 11:1:I:2:I:3 + 11:1:I:2:I:3 + 1145253 The number of transistors required using only AND, OR, and NOT gates is #transistors : NOT_gates X 2 + AND_gates X 8 + ORgates X 12 : 3X2+5><8+1>< 12:58 3.7. ((1,) X1 X2 X3 X4 f X1 X2 X3 X4 f 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 1 1 0 0 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 0 1 1 1 0 0 0 1 1 1 0 1 1 1 1 0 (b) f : 11:1:I:2:I:3:I:4 + 114113153114 + 11:1:I:2:I:3:I:4 : \$153.14 + (13:13:14 The number of transistors required using only AND, OR, and NOT gates is #transistors : NOT_gates X 2 + AND_gates X 8 + ORgates X 4 : 4x2+2><8+1><4:28 3.8. 3—3 w. m 3.10. Minimum SOP expression for f is f::@%+%%[email protected]@+ﬂﬂ : (71 + igXTg + which leads to the Circuit 3.11. Minimum SOP expression for f is which leads to the Circuit 3—4 2 1 3 3—5 3.13. 3.14. ((1,) Since VD S 2 VGS — VT the NMOS transistor is operating in the saturation region: 1 W I : —k-’ — V — V 2 D 2 n L ( GS T) MA : 10W x5>< (5V—1V)2 :800MA (b) In this case VD S < VGS — VT, thus the NMOS transistor is operating in the triode region: W 1 ID : |:(VGS — VT)VDS — §VLZJS A 1 : 20%x5x [(5V—1V)><0.2V—§><(0.2V)2 :78MA 3.15. ((1,) Since VD S g VGS — VT the PMOS transistor is operating in the saturation region: 1 W ID : ikéfU/GS — VT)2 MA : 5W x 5 X (—5V+1V)2 :400MA (b) In this case VD S > VGS — VT, thus the PMOS transistor is operating in the triode region: W 1 ID : [(VGS — VT)VDS _ EVLZJS MA 1 2 : 10W x 5 x (—5V+ 1V) >< (—0.2)V— i x (—0.2V) :39MA 3—6 3.16. W RDS : 1/ [kl/LIWGS —VT)] mA : 1/ 0.020W X 10 X (5v— 1V) : 1.25m 3.17. W RDS : 1/ [/472ow VT)] mA : 1/ [0.040 W X 10 X (3.3V — 0.66 V)] : 9479 3.18. Since VD S < (VGS — VT), the PMOS transistor is operating in the saturation region: 1 W ISD : §k;f(VGs-VT)2 MA : 50W x (—5V+1V)2:800MA Hence the value of RD S is RDS : VDS/IDS : 4.8V/800MA:6kQ 3.19. Since VD S < (VGS * VT), the PMOS transistor is operating in the saturation region: 1 W ISD : Ekény/GS—VTV MA : 80 W x (—3.3 v+ 0.66 V)2 : 558 MA Hence the value of RD S is RDS : VDS/IDS : 3.2V/558MA:5.7kQ 3.20. The low output voltage of the pseudo—NMOS inverter can be obtained by setting V1. : VD D and evaluating the voltage First we assume that the NMOS transistor is operating in the triode region while the PMOS is operating in the saturation region. For simplicity we will assume that the magnitude of the threshold voltages for both the NMOS and PMOS transistors are equal, so that VT : VTN : —VTP The current ﬂowing through the PMOS transistor is l W ID : —k/—p(—VDD —VTP)2 2 pr l : Ekp(—VDD—VTP)2 l : §kp(VDD - VT)2 3—7 Similarly, the current going through the NMOS transistor is W7% 1 ID : kgL—n [(14, — 1/}wa _ i142] l : kn |:(l/m * VTN)Vf * l : If” |:(VDD * VT)Vf i Since there is only one path for current to ﬂow, we can equate the currents ﬂowing through the NMOS and PMOS transistors and solve for the voltage Vf. 1 kaDD — VT)2 : 27% [(VDD - VTWf — gvjzl kwaD — VT)2 — 2kn(VDD — VT)Vf + knvf? : 0 This quadratic equation can be solved using the standard formula, with the parameters a, : kn, b : —2kn(VDD — VT), 0 : kp(VDD — VT)2 which gives —b _ b2 c 20, _ 40,2 a, : (VDD — VT) 2: \/(VDD — VT)2 — ﬂ(VDD — VT)2 kn k- 1:,/1——P kn Only one of these two solutions is valid, because we started with the assumption that the NMOS transistor is in the triode region while the PMOS is in the saturation region. Thus k- 1—y/1——" : (VDD — VT) Vf : (VDD - VT) 3.21. ((1,) 1 W Istat : EkéL—Z:(VDD—VT)2 i 12“A 1 5v 1v27192 A i W X X( — ) i M (5) W11 RDS : mA : 1/ [0.060W X4>< (5V—1V)] : 1.04M) (c) Using the expression derived in problem 3.20 WP MA k'p : [rig—LP : 24 —2 W” MA ' i / — : — kn i kn Ln 240 V2 VOL:Vf : (5V—1V) 240 1- 1&1 : 0.21V PD : IstatVDD : 192MA >< 5V: 960MW% 11nW RSDP : VSD/ISD : (VDD 7 W')/Istat : (5 V — 0.21 V)/0.192 mA : 24.9 m ( The low—to—high propagation delay is PLH W ./ _p kp LP VDD : 1.7x 70iF :0'99118 241\$x1x5v The high—to—low propagation delay is 1.7C PHL * l W” 1% —L“ VDD 1. iF : ﬂ : 0.1 ns 60%x4x5v 3.22. ((1,) 1 W Istat : _k'/ —p 2 P Lp MA : 48W><1><(5V—1V)2:768MA (VDD — VT)2 1/ [k;§V—;<VGS — m] mA 1/ [0.060 W X 4 X (5V— 1V)] : 1.04M) (c) Using the expression derived in problem 3.20 W A Wn A kpikéL:*96/</2kniklen i240";2 3—9 96 : r : —1 1— 1—— VOL VJ (5V V) 240] : 0.90V ((1) PD : IstatVDD : 768 MA X 5 V : 3840 MW % 3.8InW RSDP : VSD/ISD : (VDD _ T/f)/Istat : (5 V — 0.90 V)/0.768 InA : 5.34 m ( The low—to—high propagation delay is f i 1.70 ’PLH kLIZ/_:VDD 1. 1F : :X—m : 0.25 ns 96 £72 x 1 x 5 V The high—to—low propagation delay is f i 1.70 ’PHL Iggy—:VDD 1. 1F : :X—m : 0.1 ns 60 ’% x 4 x 5 V 3.23. ((1,) 1 W Istat : §k;L—p(VDD — VT)2 17 MA : 12W><1><(5V—1V)2:192MA (b) The two NMOS transistors in series can be considered equivalent to a single transistor with twice the length. Thus Wn RDS : — InA : 1/ 0.060 W x 2 X (5V— 1V) : 2.08142 (0) Using the expression derived in problem 3.20 Wp MA Wn MA . i / : _ kn 7 kn Ln 120 V2 VOL:Vf : (5V—1V) 120 1- 1&1 : 0.42V PD : IstatVDD : 192/2A >< 5V: 960MW% linW RSDP : VSD/ISD : (VDD _ T/f)/Istat : (5 V 7 0.42 V)/0.192 mA : 23.9 m ( The low—to—high propagation delay is PLH W 14/ —”V p LP DD : ﬂ : 0,9911S 24%x1x5v The high—to—low propagation delay is 1.7C ’PHL * l W” k; —L“ VDD 1.7X70iF : A—:0.2IIS 60’\‘,—2 ><2><5V 3.24. ((1,) l W Istat : _k/—p 2 P Lp MA : 12W><1><(5V—1V)2:192MA (VDD — VT)2 (b) The two NMOS transistors in parallel can be considered equivalent to a single transistor with twice the Width. Thus Wn RDS : 1/ [kLL—(VGS — VT)] InA : 1/ 0.060W X8><(5V—1V):520§2 (c) Using the expression derived in problem 3.20 Wp MA Wn MA . i / : _ kn i kn Ln 480 V2 24 : r : —1 1— 1—— VOL VJ (5v V) 4801 : 0.10V ((1) PD : IstatVDD : 192MAX5V:960MW%1H1W RSDP :: VsD/ISD : (VDD _ l/f)/Istat : (5 V — 0.10 V)/0.192 InA : 25.5 m ( The low—to—high propagation delay is 1.70 kﬂ—ji/DB 1.7 x 70 fF : —:0.99ns 241\$x1x5v PLH The high—to—low propagation delay is 1.70 PHL . W” k; —L“ VDD : ﬂ : 0.05118 60%XSX5V 3.25. ((1,) NJVIH : VOH — VIH : 0.5V NJVIL : VIL — VOL : 0.7V VOL:8><0.1V:0.8V NAIL:1V—0.8V:0.2V 3.26. Under steady—state conditions, for an n—input CMOS NAND gate the voltage levels VOL and V0 H are 0 V and VD D, respectively. No current ﬂows in a CMOS gate in the steady—state. Thus there can be no voltage drop across any of the transistors. 3.27. ((1,) PNOT_gatc : : 75 MHZ X 150 {F X (5 V)2 : 281 MW Ptoml : 0.2 X 250,000 X 281 MW : 14W 3—12 3.28. ((1,) PNOT_gatc : : 126 MHZ X 120 1F >< (3.3V)2 : 163 MW (b) PM.l : 0.2 x 260, 000 x 163 MW : 8.2 W 3.29. ((1,) The high—to—low propagation delay is 1.70 1.7 X 150 1F tpHL : /W : “A i 0.255 118 knﬁVDD 20W >< 10X5V (b) The low—to—high propagation delay is 1.70 1. 1 1F ’PLH * W * MA? X 50 i 0.638 118 kgL—IfVDD 8W><10><5V (c) For equivalent high—to—low and low—to—high delays tpHL : tpLH 1.70 i 1.70 kvaV—ijDD kLVLV—IfVDD n - n Lp * Ln i 12.5 MID i 0.5 MID 3.30. ((1,) The high—to—low propagation delay is 1.70 1.7 150 1F ML 7 / W, i A X i 0.193 118 knﬁVDD 40% X10X3.3V (b) The low—to—high propagation delay is i 1.70 1.7 X 15011“ 7 0.483118 “H k;%VDD 7 16 6—1: x 10 x 3.3V (0) For equivalent high—to—low and low—to—high delays 1 : t ’PHL PLH 1.70 i 1.70 kvav—WDD kg¥—:VDD W10 1 R L7 7 Ln i 8.75am * 0.36m 3—13 3.31. 3.32. 3.33. 3.34. 3.35. The two PMOS transistors in a CMOS NAND gate are connected in parallel. The worst case current to drive the output high happens when only one of these transistors is turned “ON”. Thus each transistor has to have the same dimensions as the PMOS transistor in the inverter, namely : P then the two transistors w L The two NMOS transistors are connected in series. If each one had the ratio W“ ratio. Thus each NMOS transistor must have could be thought of as one equivalent transistor with a T Wu i Lu T twice the width of that in the inverter, namely The two NMOS transistors in a CMOS NOR gate are connected in parallel. The worst case current to drive the output low happens when only one of these transistors is turned “ON”. Thus each transistor has to have the same dimensions as the NMOS transistor in the inverter, namely : The two PMOS transistors are connected in series. If each of these transistors had the ratio then the P two transistors could be thought of as one transistor with a WP ratio. Thus each PMOS transistor must be 2Lp Wu i L“ 7 8. made twice as wide as that in the inverter, namely The worst case path in the PMOS network contains two transistors in series. Thus each PMOS transistor must be twice as wide the transistors in the inverter. The worst case path in the NMOS network also contains two transistors in series. Similarly, each NMOS transistor must be twice as wide as those in the inverter. The worst case PMOS path contains three transistors in series so each transistor must be three times as wide as the PMOS transistors in the inverter. The worst case NMOS path contains two transistors in series. Thus the NMOS transistors must be two times as wide. ((1,) The current ﬂowing through the inverter is equal to the current ﬂowing through the PMOS transistor. We shall assume that the PMOS transistor is operating in the saturation region. % l Istat : LP (VGS _ VTp)2 MA 2 : 120— ><((3.5V—5V)+1V):30MA V2 (b) The current ﬂowing through the NMOS transistor is equal to the static current I Stat. Assume that the NMOS transistor is operating in the triode region. W” 1 Istat : [(VGS _ VTn)VDS _ MA 1 30m : 240 W X [2.5V >< Vf — i142] 1 : 20V} — 4sz Solving this quadratic equation yields Vf : 0.05 V. Note that the output voltage Vf satisﬁes the assumption that the PMOS transistor is operating in the saturation region while the NMOS transistor is operating in the triode region. The static power dissipated in the inverter is PS : IMVDD : 30 MA x 5 v : 150 MW (d) The static power dissipated by 250,000 inverters. 2507 000 X P5 : 37.5 W 3—14 3.36. NOR plane NOR plane 3.37. NOR plane NOR plane 3—15 3.38. NOR plane NOR plane D VD 3.39. NOR plane NOR plane D V0 3—16 NOR plane 3.40. NOR plane NOR plane 3.41. NOR plane 3—17 3.42. f2 : m 1 f2 : mg f2 : rm f 2 : T" 7 f2 : m1 W m2 f2 : m1 W m4 f2 : m1 W m7 f2 : m2 W m4 f2 : m2 W m7 f2 : m4 W m7 f2 : m1 W m2 W m4 f2 : m1 W m2 W m7 f2 : m1 W m4 W m7 f2 : m2 W m4 W m7 f2 : m1 W m2 W m4 + m7 3.43. f2 : mg f2 : n23 f2 : m 5 f2 : n26 f2 : m0 W m3 f2 : m0 W m5 f2 : m0 W m6 f2 : m3 W m4 f2 : m3 W m6 f2 : m5 W m6 f2 : m0 W m3 W m5 f2 : m0 W m3 W m6 f2 : m0 W m5 W m6 f2 : m3 W m5 W m6 f2 : m0 W m3 W m5 + m6 3—18 3.44. XII—(2 + X1X3 + X2)_(3 3.45. The canonical SOP for f is f : Ely/9T3 + \$111313 + 11:1E2T3 + 11:11:2E3 + 11:1:I:2:I:3 This expression can be manipulated into f : E1:I:2+:I:153+:I:1:I:2 : 11:2 + 11:13; The circuit is 3.46. The canonical SOP for f is f : 11:11:qu + 11:23:3T4 + Eligig This expression can be manipulated into f : 11:2 - (114114 + 11354) + \$2 - (51:1:3) Using functional decomposition we have f : 1152f1 + 52102 Where f1 : 11:115.; +3354 f2 : 511153 The circuit is X1X2X4 + X2X3)_(4 + XII—(2)73 3.47. The canonical SOP for f is f : 11:11:qu + 11:23:354 + 515253 This expression can be manipulated into f : 11:2 - (114114 + 11:3T4) + \$2 - Using functional decomposition we have f : 11:2f1 + ng2 Where f1 : 11:1:I:4+:I:3T4 f2 : 511153 The function f1 requires one Z—LUT, While f2 requires three Z—LUTs. We then need three additional 3—LUTs to realize f , as illustrated in the circuit X1X2X4 + X3X2X4 X1X2X4 + X2X3)_(4 + XII—(2)73 3.48. g : 72:1:3 h : I 1 j : 11:2 k : 11:3 3.49. ((1,) 3(3X1X2 + X3 01 = X1X2 + X3 27300+X3(X1+X2) = X1X3+X2X3 3.50. ((1,) 3—21 3.51. 3.52. 3.53. 3.54. 3.55. X1X2X4 . X1. X2X33f4 = X1X2X4 + X1+ X2X3X4 module prob2_51 (x1, x2, x3, x4, f); input x1,x2,x3,x4; output f; assign f: (x2 & ~x3 & ~x4) | (~x1& x2 & x4) | (~x1& x2 & x3) | (x1 & x2 & X3); endmodule module prob2_52 (x1, x2, x3, x4, f); input x1,x2,x3,x4; output f; assign f: (x1 | x2 | ~x4) & (~x2 | x3 | ~x4) & (~x1 | x3 | ~x4) & (~x1 | ~x3 | ~x4); endmodule module prob2_53 (x1, x2, x3, x4, x5, x6, x7, f); input x1, x2, x3, x4, x5, x6, x7; output f; assignf= (Xl &X3&~X6) | (X1 &X4 &X5 &~X6) | (X2&X3 &X7) | (X2 &X4 &X5 &X7); endmodule The circuit in Figure P310 is a two—input XOR gate. Since NMOS transistors are used only to pass logic 0 and PMOS transistors are used only to pass logic 1, the circuit does nor suffer from any major drawbacks. The circuit in Figure P3. 11 is a two—input XOR gate. This circuit has two drawbacks: when both inputs are 0 the PMOS transistor must drive f to 0, resulting in f : VT volts. Also, when 11:1 : l and 11:2 : 0, the NMOS transistor must drive the output high, resulting in f : VD D — VT. 3—22 ...
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Brown & Vranesic - Fundamentals of Digital Logic with VHDL (2nd) --solution chap3

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