Problems - 1 ECEN5827 x erg/l 1’ 72am 3" 2/12 1. [15...

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Unformatted text preview: 1 ECEN5827 x erg/l 1’ 72am 3" 2/12 1. [15 points] An inverter circuit is shown in Figure l. The device W/L ratios are given in the figure and the device parameters are given below. Answer the following questions. NMOS: MC” = IOOM/Vz, Vm 21V, yn z 0, an m 0.01[V“] PMOS: upcox =25/1A/V2, le =1V, yp err/1p zoom/‘1] Il Figure 1 0\/ 21/ {V 61/ W 21/ HV‘;[/ 9] Draw in approximate curves on the axes given above for V0 vs V; and I, vs V1 for 0 S V1 S 5V . Label the operating modes of each device on the V0 vs V; plot for each region. On the V0 vs VI plot, label the input voltage V1 at the point where VO = 2.5 V. On the I] vs V1 plot, label the input voltage V1 at the point where I] is equal to its peak value. Solve and label the approximate peak value of l]. 2 2 K2: "K, C9 lémeM 007/4 adrue => 10! :fl/Vr61~bé>:'zéz— flz (1%” #4) I7:*/ (a) f—'| gm(vf~4):mo-vf ~14) :> l/f: Voo‘Vé +z/WV1 ,3)! Mfr—IT / fir: /Va. (VJ—VH2 : QSaw' (b) [6] At the dc operating point where Vo = 2.5 V, solve for the approximate low frequency gain A” = v“ /v,. and output resistance, Rout. 9/“— xtwi NM _ <~l 7); Km“ %:£_EI7I:QW:XSM/V <7”??? i Jzo‘l/J?” gm” Q (gm: Shagwfl/V 2 3 AH Mamet/6w :1? Final Exam, 12/13/10 R2, UCB, Fall 2010 ECEN 5827 3/12 2. [% pts] In the CMOS op-amp shown in Fig. 2, the transistor parameters are: 1% NMOS: ,unCox = 40 uA/Vz, Vm = 0.4 V, yn m 0, 1,, w 0 (small, but results in Rout listed) PMOS: prox = 20 uA/Vz, th = —0.4 V, Y}; z 0, it], w 0 (small, but results in Rom listed) You can assume that the DC bias current sources 13 = 131 = 132 = 10 uA, and the DC bias voltage sources VBIASl, VBIASZ, are ideal. The small-signal open—loop transfer function of the op-amp is A(s) = vo/(v(+)—v(—)), and the small-signal output resistance is R out~ M12 1000/1 7 i012 lav/“Al M13 1000/1 -—VSS=—l.6V Figure 2: CMOS op—amp, [B = 131 = 132 = 10 uA. Rout = 50 M9, A(s) = vo/(v(+)—v(—)). a) [2] Label + and — input in Fig. 2. b) [3] Assuming the DC input and output voltages are V(+) = V(—) = V0 = O, VBIASl and VBIAS2 are such that all transistors are in the active/saturation region, find the small—signal parameters gml, gm 10 and gm13. gm: w 24/ /,m .2 My f pf/z fin/a: 2’” /-————\ Final Exam, 12/13/10 RZ, UCB, Fall 2010 ECEN 5827 4/12 0) [6] Find Via/AS] and ngg to maximize output voltage swing of the op-amp. Then find the boundaries of the output voltage swing, VOW-n, VOmax (116. the range of output voltages such that all devices stay in the active/saturation region). For each of the two boundaries, specify which transistors (or transistor) are at the triode boundary. 1 9 — - .— - VIE/‘sz : I/éS/o 1’- Iévg: V; + Z 16:" ’ Qéy [Ky 1V 6/55) V345,: 1/0,) ~ Vol/,2 4/5493 : [5V*&,6V3 LU! M l/0l/17a7:.: (MIR— Trials-2°”): V695“! ’L/Vép/ : /' Hy Vanna/L 2 Mbawa}; l/anz/ 1/5“ 3- “XL/V M /——' d) [6] At the DC operating point found in part (b), the small-signal (lie. incremental) output resistance of \A the op—amp is Rout = 50 M9. Solve for the low-frequency gain A(O). c) 4(0): /¢(o): Zfl (low/Mm”) 2’W .3 Wwa : my”? /0&%4> Final Exam, 12/13/10 RZ, UCB, Fall 2010 ECEN 5827 5/12 .1 g, S e) [3] Suppose that the devices in the op-amp of Fig. 2 have A” = A], = 9». Given Rout = 50 MS), find the channel-length modulation parameter 9». J. /. jg: vi— >> Z .: a/EZL » ’40} )‘IO Zia/3 o/O/awc [C a; 7LAc av/jga/ MWZC (on; ,‘m/Qm Mad/e] I; : 0272 50+ J 65W: we) 7% ; 2&0 £6: 2:;zjwMM 3% 7g) :4: 2w // 2 , /4 Final Exam, 12/13/10 R2, UCB, Fall 2010 ECEN 582 7 6/12 3. [25 points] A CMOS op—amp is characterized with the open—loop transfer function given below and has an output resistance of Row. 20 AOL (S) = :0 = A0 'd Hi] 1+i mp1 mp2 A0 =100dB fp2 =5MHZ fpl 2?’ Raul :? (a) [10] With the op—amp in the feedback configuration shown in Fig. 3 and a load capacitance of C L = 40 pF , the closed—loop bandwidth of the system is BW= 100 kHz and the phase margin is ¢M = 75° (you can assume that R >> Rom). Solve for the open—loop op-amp dominant pole frequency jg, and output resistance, R 011/ - ‘ 1 7(5): / ' J»./4OL(;): ,KZE. / jfi' “Z4 /5 /o (/ 147%)(H affix/7‘ 2%) erflJCL (2‘5"? *‘ 7/1; whee P2427)” 2> 75;! r @612 /0 (IO—F";— flw WMf—z/W'TSSW/Mfg?) {Let/{ii} 41/;0": 75’" e 7E = (7% 161/2: 7C: 5L6?» «70': day/760 1175:“ capacitance ' order to maintain a phase margin of ¢M 2 75°. inal Exam, 12/13/10 R2, UCB, Fall 2010 ECEN 5827 7/12 (p?) [10] With the op—amp in the non—inverting, unity-gain configuration with a load capacitance of C L = 40pF , complete é the following: o Solve for the phase margin & state whether the closed loop response has complex poles or all real poles. 0 Sketch approximate bode plots of the magnitude response of the loop gain lT‘ and closed—loop gain [Ami (in dB on y-axis and log frequency on x—axis). Label the key salient features of the bode asymptotes. 0 Sketch the output response to a step input, including the key features of any overshoot, ringing (and ringing frequency if there is any), and relative damping (e. g. is it under—damped, critically damped, or overdamped). 7(5): étés)‘ 4"“ 75: Va; K413 Ma ’ PM: 950 CL-Polesr all real? 9> 75% : 700—fawd(i§;>”fiamd g I am 6w: W «> 76w? 71 may; a. __ a L 0h j: 2> 1;: Male W2 9&4— 7a—mu +2 Final Exam, 12/13/10 RZ, UCB, Fall 2010 ECEN 5827 8/12 4. [20 pts] Figure 4 shows a current mirror that serves as a small-signal current amplifier. The transistor parameters are: NMOS: ,unCox = 40 uA/VZ, Vm : 0.4 v, y” z 0, 2,, z 0. The input current source has a DC bias component [IN = 5 uA. The output is connected to an ideal DC bias voltage source VB: 0.5 V. At this DC operating point, the parasitic capacitances of M1 are Cgsl = 0.2 pF, ng1 = 0.02 pF, Cdbl = 0.1 pF, and C5“ = 0.1 pF, and the current amplifier small—signal transfer function can be written as: bi Am = l?!" = A<0>1+bls = Am) ‘0: z," l+als 1+: a) You can assume that all device arasitic ca acitances are r0 ortional to the channel Width. [OUT + lout [IN + [in 7' Figure 4: Current amplifier, [IN = 5 uA. a, )L #(07: Eff: /0 4.1:“ j” g )1 a) [4] Find the low-frequency current gain A(O). Wficcapaefianeesomif/ '4‘” “7" (“/5 05 M/ t ,- [7523 Zfl/Z/ dei: ‘(dfiz " [Sb 2 ’fl/r- 6 / A ,d) Lug/Using the N—EET, find expressions for fl, and fl. No credit will be given to other approaches to finding A(s). To get full credit, show the equivalent circuit models and the test setups used to find all and 191. (Note that the output is current 1'01”; therefore, “nulling the output” means that the input im and a test source are adjusted so that 10m —> O). mew Final Exam, 12/13/10 RZ, UCB, Fall 2010 ECEN 5827 9/12 Prob. 4: Continued (space for part c) Final Exam, 12/13/10 RZ, UCB, Fall 2010 ECEN 5827 10/12 5. [15 pts] Figure 5 shows a current mirror designed to generate a dc bias current IREF= 10 uA through a variable-resistance load Rzoad. The transistor parameters are: NMOS: ,unCox = 40 uA/Vz, Vm = 0.4 V, y” z 0, 2n = (0.1) l/V. VDD = +3 .2v Figure 5: Current mirror a) [6] Assuming that Rload is such that all devices operate in the active/saturation region, find R so that [REF = 10 uA. State any approximations you made. V6: law 4&4 2f??? :WMN /’/ ‘ 656,; g , VKM. .. V 5:) 3 V00 5‘2 : 9'2 f4 f“ %. b) [3] Suppose that R has a large positive temperature coefficient. Is the temperature coefficient of [REF positive or negative? Justify your answer. jfi’flfigi 9 W / ¢> 756%): — my?) Final Exam, 12/13/10 r RZ, UCB, Fall 2010 ECEN 5827 11/12 0) [6] Assuming all devices operate in the active/saturation region, find an expression for and compute the small-signal (incremental) output resistance Rom. 55M Final Exam, 12/13/1 0 RZ, UCB, Fa112010 ...
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This note was uploaded on 11/07/2011 for the course ECEN 5827 taught by Professor Staff during the Spring '08 term at Colorado.

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Problems - 1 ECEN5827 x erg/l 1’ 72am 3" 2/12 1. [15...

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