MIT6_004s09_lec06

# MIT6_004s09_lec06 - MIT OpenCourseWare http://ocw.mit.edu...

This preview shows pages 1–4. Sign up to view the full content.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: MIT OpenCourseWare http://ocw.mit.edu For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms . 6.004 Computation Structures Spring 2009 L06 – FSMs 1 6.004 – Spring 2009 2/24/09 (Synchronous) Finite State Machines Lab 2 is due Thursday Great - Theory! Finally! Some ENGINEERING! modified 2/23/09 09:27 L06 – FSMs 2 6.004 – Spring 2009 2/24/09 Our New Machine Combinational Logic Current State New State Input Output Clock State Registers k k m n • Acyclic graph • Obeys static discipline • Can be exhaustively enumerated by a truth table of 2 k+m rows and k+n output columns • Engineered cycles • Works only if dynamic discipline obeyed • Remembers k bits for a total of 2 k unique combinations L06 – FSMs 3 6.004 – Spring 2009 2/24/09 Must Respect Timing Assumptions! Questions: • Constraints on T CD for the logic? • Minimum clock period? • Setup, Hold times for Inputs? Combinational Logic Current State New State Input Output Clock t CD,L = ? t PD,L = 5ns t CD,R = 1ns t PD,R = 3ns t S,R = 2ns t H,R = 2ns t CD,L > 1 ns t S = t PD,L + t S,R = 7 nS t H = t H,R- t CD,L = 1 nS We know how fast it goes… But what can it do? t CD,R (1 ns) + t CD,L (?) > t H,R (2 ns) t CLK > t PD,R +t PD,L + t S,R > 10nS L06 – FSMs 4 6.004 – Spring 2009 2/24/09 A simple sequential circuit… Lets make a digital binary Combination Lock: Specification: • One input ( “0” or “1”) • One output (“Unlock” signal) • UNLOCK is 1 if and only if: Last 4 inputs were the “combination”: 0110 How many registers do I need? Lock IN U CLK L06 – FSMs 5 6.004 – Spring 2009 2/24/09 Abstraction du jour: Finite State Machines • A FINITE STATE MACHINE has Clocked FSM m n • k STATES: S 1 … S k (one is “initial” state) • m INPUTS: I 1 … I m • n OUTPUTS: O 1 … O n • Transition Rules s’(s, I) for each state s and input I • Output Rules Out(s) for each state s L06 – FSMs 6 6.004 – Spring 2009 2/24/09 State Transition Diagram SX U=0 S0 U=0 S01 U=0 1 S011 U=0 1 S0110 U=1 1 1 1 XXX U=0 NAME of state OUTPUT when in this state INPUT causing transition Heavy circle Means INITIAL state Designing our lock … • Need an initial state; call it SX....
View Full Document

## This note was uploaded on 11/07/2011 for the course COMPUTER S 6.004 taught by Professor Staff during the Spring '09 term at MIT.

### Page1 / 8

MIT6_004s09_lec06 - MIT OpenCourseWare http://ocw.mit.edu...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online