MIT6_004s09_lec15 - MIT OpenCourseWare http/ocw.mit.edu 6.004 Computation Structures Spring 2009 For information about citing these materials or our

MIT OpenCourseWare http://ocw.mit.edu For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms . 6.004 Computation Structures Spring 2009

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L15 – Memory Hierarchy 1 6.004 – Spring 2009 4/2/09 The Memory Hierarchy Lab #5 due tonight L15 – Memory Hierarchy 2 6.004 – Spring 2009 4/2/09 What we want in a memory PC INST MADDR MDATA BETA MEMORY Capacity Latency Cost Register 100’s of bits 20 ps $$$$ SRAM 100’s Kbytes 1 ns $$$ DRAM 100’s Mbytes 40 ns $ Hard disk* 100’s Gbytes 10 ms ¢ Want 1’s Gbytes 1 ns cheap * non-volatile ADDR DOUT ADDR DIN/DOUT L15 – Memory Hierarchy 3 6.004 – Spring 2009 4/2/09 SRAM Memory Cell 6-T SRAM Cell word line N bit bit access FETs static bistable storage element word line N+1 There are two bit-lines per column: one supplies the bit, the other it’s complement. On a Read Cycle: A single word line is activated (driven to “1”), and the access transistors enable the selected cells, and their complements, onto the bit lines. 0 1 1 Good, but slow 0 Slow and almost 1 Strong 1 Strong 0 Doesn’t this violate our static discipline? Writes are similar to reads, except the bit-lines are driven with the desired value of the cell. The writing has to “overpower” the original contents of the memory cell. L15 – Memory Hierarchy 4 6.004 – Spring 2009 4/2/09 Multiport SRAMs (a.k.a. Register Files) One can increase the number of SRAM ports by adding access transistors. By carefully sizing the inverter pair, so that one is strong and the other weak, we can assure that our WRITE bus will only fight with the weaker one, and the READs are driven by the stronger one - thus minimizing both access and write times. write read0 read1 PU = 2 / 1 PD = 4 / 1 PU = 2 / 2 PD = 2 / 3 4/1 5 / 1 2 / 1 2 / 1 wd rd1 rd0 This transistor isolates the storage node so that it won’t ﬂip unintentionally.

L15 – Memory Hierarchy 5 6.004 – Spring 2009 4/2/09 1-T Dynamic Ram word line bit access FET C in storage capacitor determined by: C = A d more area better dielectric thinner film 1-T DRAM Cell V REF Explicit storage capacitor Six transistors/cell may not sound like much, but they can add up quickly. What is the fewest number of transistors that can be used to store a bit?