MIT6_004s09_lec16

MIT6_004s09_lec16 - MIT OpenCourseWare http:/ocw.mit.edu...

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MIT OpenCourseWare http://ocw.mit.edu For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms . 6.004 Computation Structures Spring 2009
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L16 – Cache Issues 1 6.004 – Spring 2009 4/7/09 Cache Issues Cache miss Why the book? Lecture notes are faster! modified 4/6/09 14:12 Quiz #3 Friday! L16 – Cache Issues 2 6.004 – Spring 2009 4/7/09 Basic Cache Algorithm ON REFERENCE TO Mem[X]: Look for X among cache tags. .. HIT: X = TAG(i) , for some cache line i ± READ: return DATA(i) ± WRITE: change DATA(i); Start Write to Mem(X) MISS: X not found in TAG of any cache line ± REPLACEMENT SELECTION: ± ± Select some line k to hold Mem[X] (Allocation) ± READ: Read Mem[X] Set TAG(k)=X, DATA(K)=Mem[X] ± WRITE: Start Write to Mem(X) Set TAG(k)=X, DATA(K)= new Mem[X] MAIN MEMORY CPU (1 ! ±) Tag Data A B Mem[A] Mem[B] L16 – Cache Issues 3 6.004 – Spring 2009 4/7/09 Cache Design Issues Associativity – a basic tradeoff between ± Parallel Searching (expensive) vs ± Constraints on which addresses can be stored where Replacement Strategy: ± OK, we’ve missed. Go±a add this new address/value pair to the cache. What do we kick out? ± ± Least Recently Used: discard the one we haven’t used the longest. ± ± Plausible alternatives, (e.g. random replacement. Block Size: ± Amortizing cost of tag over multiple words of data Write Strategy: ± When do we write cache contents to main memory? L16 – Cache Issues 4 6.004 – Spring 2009 4/7/09 Associativity 0 1 Fully Associative - ± expensive! - ± flexible: any address can be cached in any line Lots. .. ... or NONE! Direct Mapped - ± cheap (ordinary SRAM) - ± contention: addresses compete for cache lines
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L16 – Cache Issues 5 6.004 – Spring 2009 4/7/09 Loop B: Pgm at 1024, data at 2048: … but not here! Loop A: Pgm at 1024, data at 37: Works GREAT here… Direct-Mapped Cache Contention Assume 1024-line direct- mapped cache, 1 word/line. Consider tight loop, at steady state: (assume WORD, not BYTE, addressing) Memory Address 1024 37 1025 38 1026 39 1024 ... 1024 2048 1025 2049 1026 2050 1024 ... Cache Line 0 37 1 38 2 39 0 0 0 1 1 2 2 0 Hit/ Miss HIT HIT HIT HIT HIT HIT HIT MISS MISS MISS MISS MISS MISS MISS We need some associativity, But not full associativity… L16 – Cache Issues 6 6.004 – Spring 2009 4/7/09 Fully-assoc. vs. Direct-mapped Fully-associative N-line cache: ± N tag comparators, registers used for tag/data storage ($$$) ± Location A might be cached in any one of the N cache lines; no restrictions! ± Replacement strategy (e.g., LRU) used to pick which line to use when loading new word(s) into cache ± PROBLEM: Cost! Direct-mapped N-line cache: ± 1 tag comparator, SRAM used for tag/data storage ($) ± Location A is cached in a specific line of the cache determined by its address; address “collisions” possible ± Replacement strategy not needed: each word can only be cached in one specific cache line ± PROBLEM: Contention! L16 – Cache Issues
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This note was uploaded on 11/07/2011 for the course COMPUTER S 6.004 taught by Professor Staff during the Spring '09 term at MIT.

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MIT6_004s09_lec16 - MIT OpenCourseWare http:/ocw.mit.edu...

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