MIT6_004s09_lec20

MIT6_004s09_lec20 - MIT OpenCourseWare http/ocw.mit.edu...

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MIT OpenCourseWare http://ocw.mit.edu For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms . 6.004 Computation Structures Spring 2009
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L20 – Communication 1 6.004 – Spring 2009 4/23/09 Interconnect & Communication Space, Time, & stuff… Quiz #4 tomorrow! modified 4/22/09 11:14 L20 – Communication 2 6.004 – Spring 2009 4/23/09 Computer System Technologies What’s the most important part of this picture? Mother boards SDRAM LAN technology Linux Window s XP Hard Disk Drives DRAM Flash Memory Graphics Acceleration ActiveX Controls App Servers L20 – Communication 3 6.004 – Spring 2009 4/23/09 Technology comes & goes; interfaces last forever Interfaces typically deserve more engineering a±ention than the technologies they interface… ± Abstraction: should outlast many technology generations ± Often “virtualized” to extend beyond original function (e.g. memory, I/O, services, machines) ± Represent more potential value to their proprietors than the technologies they connect. Interface sob stories: ± Interface “warts”: Windows “aux.c” bug, Big/liTle Endian wars ± IBM PC debacle ... and many success stories: ± IBM 360 Instruction set architecture; Postscript; Compact Flash; . .. ± Backplane buses L20 – Communication 4 6.004 – Spring 2009 4/23/09 CPU MEM I/O DISK I/O MEM Ancient Times (Ad hoc connections) System Interfaces & Modularity Late 60s (Processor-dependent Bus) CPU MEM I/O DISK I/O MEM ? 80s (Processor-independent Bus) CPU CPU I/O DISK I/O MEM Today Buses Galore MEM MEM CPU DISK I/O I/O L2/L3 $ Graphics I/O “AGP” bus Front-side bus Back-side bus Bridge
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L20 – Communication 5 6.004 – Spring 2009 4/23/09 Interface Standard: Backplane Bus Modular cards that plug into a common backplane: CPUs Memories Bulk storage I/O devices S/W? The backplane provides: Power Common system clock Wires for communication L20 – Communication 6 6.004 – Spring 2009 4/23/09 The Dumb Bus: ISA & EISA Original primitive approach -- Just take the control signals and data bus from the CPU module, buffer it, and call it a bus. ISA bus (Original IBM PC bus) - Pin out and timing is nearly identical to the 8088 spec. Ah, you forget, Unibus, S-100, SWTP SS-50, STB, MultiBus, Apple 2E, … L20 – Communication 7 6.004 – Spring 2009 4/23/09 Smarter “Processor Independent” Buses NuBus, PCI… Isolate basic communication primitives from processor architecture: ± Simple read/write protocols ± Symmetric: any module can become “Master” (smart I/O, multiple processors, etc) ± Support for “plug & play” expansion Goal: vendor-independent interface standard TERMINOLOGY – BUS MASTER – a module that initiates a bus transaction.
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This note was uploaded on 11/07/2011 for the course COMPUTER S 6.004 taught by Professor Staff during the Spring '09 term at MIT.

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MIT6_004s09_lec20 - MIT OpenCourseWare http/ocw.mit.edu...

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