MIT6_004s09_lec22

MIT6_004s09_lec22 - MIT OpenCourseWare http:/ocw.mit.edu...

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MIT OpenCourseWare http://ocw.mit.edu For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms . 6.004 Computation Structures Spring 2009
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L22 – Pipelining the Beta 1 6.004 – Spring 2009 4/30/09 Pipelining the Beta bet±ta ('be-t&) n. Any of various species of small, brightly colored, long-finned freshwater fishes of the genus Betta, found in southeast Asia. be±ta (‘b A- t&, ‘b E -) n. 1. The second letter of the Greek alphabet. 2. The exemplary computer system used in 6.004. I don’t think they mean the fish. .. maybe they’ll give me partial credit. .. modified 4/27/09 11:17 Lab #7 due Tonight! L22 – Pipelining the Beta 2 6.004 – Spring 2009 4/30/09 CPU Performance We’ve got a working Beta… can we make it fast? MIPS = Millions of Instructions/Second Freq = Clock Frequency, MHz CPI = Clocks per Instruction MIPS = Freq CPI To Increase MIPS: 1. DECREASE CPI. - RISC simplicity reduces CPI to 1.0. - CPI below 1.0? Tough. .. you’ll see multiple instruction issue machines in 6.823. 2. INCREASE Freq. - Freq limited by delay along longest combinational path; hence - PIPELINING is the key to improved performance through fast clocks. L22 – Pipelining the Beta 3 6.004 – Spring 2009 4/30/09 Beta Timing New PC PC+4 Fetch Inst. Control Logic Read Regs RA2SEL mux ASEL mux BSEL mux ALU Fetch data +OFFSET WDSEL mux RF setup PC setup Mem setup PCSEL mux =0? CLK ± CLK ± Wanted: longest paths Complications: ± some apparent paths aren’t “possible” ± operations have variable execution times (eg, ALU) ± time axis is not to scale (eg, t PD,MEM is very big!) “precedence graph” ALU +OFFSET LD(R1,10,R0) LDR(X,R3) L22 – Pipelining the Beta 4 6.004 – Spring 2009 4/30/09 Why isn’t this a 20-minute lecture? 1. The Beta isn’t combinational… ± ± Explicit state in register file, memory; ± ± Hidden state in PC. 2. Consecutive operations – instruction executions – interact: ± Jumps, branches dynamically change instruction sequence ± Communication through registers, memory Our goals: ± Move slow components into separate pipeline stages, running clock faster ± Maintain instruction semantics of unpipelined Beta as far as possible We’ve learned how to pipeline combinational circuits. What’s the big deal? ± ±
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L22 – Pipelining the Beta 5 6.004 – Spring 2009 4/30/09 Ultimate Goal: 5-Stage Pipeline GOAL: Maintain (nearly) 1.0 CPI, but increase clock speed to barely include slowest components (mems, regfile, ALU) APPROACH: structure processor as 5-stage pipeline: IF Instruction Fetch stage : Maintains PC, fetches one instruction per cycle and passes it to WB Write-Back stage : writes result back into register file.
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This note was uploaded on 11/07/2011 for the course COMPUTER S 6.004 taught by Professor Staff during the Spring '09 term at MIT.

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MIT6_004s09_lec22 - MIT OpenCourseWare http:/ocw.mit.edu...

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